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A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator Journal article
Zhang, Hongshuai, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator[J]. IEEE Journal of Solid-State Circuits, 2023, 58(12), 3565-3575.
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:2 TC[Scopus]:4  IF:4.6/5.6 | Submit date：2024/01/02
Analog-to-digital Converter (Adc)  Auxiliary Noise Shaping (Ns) Successive-approximation Register (Sar) Adc  Capacitor Stacking  Data-weighted Averaging And detect-And-skip (Dwa And Das)  Differential Sampling  Energy Efficient  Error SupprEssion (Es) And Reconstruction  Gain Error Shaping (Ges)  Partial Time Interleaving  Passive Ns  Pipelined Sar  Quantization Predication Unrolled  Two-step Floating Inverter Amplifier (Fia)  
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier Journal article
Jiang,Wenning, Chen,Chixiao, Liu,Qi, Liu,Ming, Zhu,Yan, Chan,Chi Hang, Xu,Hao, Martins,Rui P.. A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier[J]. IEEE Journal of Solid-State Circuits, 2023, 58(10), 2709 - 2721.
Authors:  Jiang,Wenning;  Chen,Chixiao;  Liu,Qi;  Liu,Ming;  Zhu,Yan; et al.
Favorite | TC[WOS]:4 TC[Scopus]:3  IF:4.6/5.6 | Submit date：2023/08/03
Adaptive Bias  Analog-to-digital Converter (Adc)  Floating Inverter Amplifier (Fia)  Pipelined-successive-approximation-register (Sar) Adc  Reference Ripple Cancellation (Rrc)  Reference Ripple Neutralization (Rrn)