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An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications Journal article
Cao, Rujian, Zhao, Zhongyu, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications[J]. IEEE Transactions on Circuits and Systems II-Express Briefs, 2024, 71(11), 4688-4692.
Authors:  Cao, Rujian;  Zhao, Zhongyu;  Un, Ka Fai;  Yu, Wei Han;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/10/10
Sparse Matrices  Computational Modeling  Transformers  Hardware  Energy Efficiency  Circuits  Throughput  Dataflow  Digital Accelerator  Energy-efficient  Field-programmable Gate Array (Fpga)  Sparsity  Transformer  
N-AquaRAM: A Cost-Efficient Deep Learning Accelerator for Real-Time Aquaponic Monitoring Journal article
Siddique, Ali, Iqbal, Muhammad Azhar, Sun, Jingqi, Zhang, Xu, Vai, Mang I., Siddique, Sunbal. N-AquaRAM: A Cost-Efficient Deep Learning Accelerator for Real-Time Aquaponic Monitoring[J]. Agricultural Research, 2024.
Authors:  Siddique, Ali;  Iqbal, Muhammad Azhar;  Sun, Jingqi;  Zhang, Xu;  Vai, Mang I.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:1.4/1.5 | Submit date：2024/10/10
Aquaculture  Deep Learning Accelerator  Field Programmable Gate Arrays (Fpgas)  Fish Size Estimation  Giga OPerations Per Second (Gops)  Smart Aquaponics  
An Outphase-Interleaved Switched-Capacitor Hybrid Buck Converter with Relieved Capacitor Inrush Current and COUT-Free Operations Journal article
Zhang, Xiongjie, Ma, Qiaobo, Jiang, Yang, Zhao, Anyang, Law, Man Kay, Martins, Rui P., Mak, Pui In. An Outphase-Interleaved Switched-Capacitor Hybrid Buck Converter with Relieved Capacitor Inrush Current and COUT-Free Operations[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024, 59(4), 1078-1092.
Authors:  Zhang, Xiongjie;  Ma, Qiaobo;  Jiang, Yang;  Zhao, Anyang;  Law, Man Kay; et al.
Favorite | TC[WOS]:3 TC[Scopus]:3  IF:4.6/5.6 | Submit date：2024/05/02
Capacitor Inrush Current  Hybrid Buck  Inductor Current Reduction  On-chip Gate Driver (Gd)  Output Capacitor Free  
A 24-V-Input Highly Integrated Interleaved-Inductor Multiple Step-Down Hybrid DC–DC Converter With Inherent Current Equalization Characteristics Journal article
Zhang, Xiongjie, Zhao, Anyang, Ma, Qiaobo, Jiang, Yang, Law, Man Kay, Martins, Rui P., Mak, Pui In. A 24-V-Input Highly Integrated Interleaved-Inductor Multiple Step-Down Hybrid DC–DC Converter With Inherent Current Equalization Characteristics[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024.
Authors:  Zhang, Xiongjie;  Zhao, Anyang;  Ma, Qiaobo;  Jiang, Yang;  Law, Man Kay; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/05/16
Dc–dc Converter  Fully Symmetric  High Step-down  Hybrid Topology  Interleaved Inductor  On-chip Gate Driver (Gd)  
A Quad-Slope 70V GaN Gate Driver with Integrated Three-Mode Level Shifter for Enhanced Negative Voltage Tolerance, dV/dt Detection and Double-Edge Self-Triggered Delay Compensation Conference paper
Liu, Tianqi, Gao, Qiang, Martins, Rui P., Lu, Yan. A Quad-Slope 70V GaN Gate Driver with Integrated Three-Mode Level Shifter for Enhanced Negative Voltage Tolerance, dV/dt Detection and Double-Edge Self-Triggered Delay Compensation[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 1141-1145.
Authors:  Liu, Tianqi;  Gao, Qiang;  Martins, Rui P.;  Lu, Yan
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/06/05
Delay Compensation  Dv/dt Detection  Gan  Gate Driver  Negative Voltage  
Modeling Attack Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability Journal article
Xu, Chongyao, Zhang, Litao, Law, Man Kay, Zhao, Xiaojin, Mak, Pui In, Martins, Rui P.. Modeling Attack Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability[J]. IEEE Internet of Things Journal, 2023, 10(18), 16300 - 16315.
Authors:  Xu, Chongyao;  Zhang, Litao;  Law, Man Kay;  Zhao, Xiaojin;  Mak, Pui In; et al.
Favorite | TC[WOS]:10 TC[Scopus]:15  IF:8.2/9.0 | Submit date：2023/08/03
Field-programmable Gate Array (Fpga)  Machine Learning (Ml) Modeling Attack  Obfuscated Interconnection (Oi)  Physical Unclonable Function (Puf)  
Atomically precise vacancy-assembled quantum antidots Journal article
Fang, Hanyan, Mahalingam, Harshitra, Li, Xinzhe, Han, Xu, Qiu, Zhizhan, Han, Yixuan, Noori, Keian, Dulal, Dikshant, Chen, Hongfei, Lyu, Pin, Yang, Tianhao, Li, Jing, Su, Chenliang, Chen, Wei, Cai, Yongqing, Neto, A. H.Castro, Novoselov, Kostya S., Rodin, Aleksandr, Lu, Jiong. Atomically precise vacancy-assembled quantum antidots[J]. Nature Nanotechnology, 2023, 18(12), 1401-1408.
Authors:  Fang, Hanyan;  Mahalingam, Harshitra;  Li, Xinzhe;  Han, Xu;  Qiu, Zhizhan; et al.
Favorite | TC[WOS]:17 TC[Scopus]:17  IF:38.1/39.6 | Submit date：2024/01/02
Hot-electron Generation  Logic Gate  Semiconductor  Graphene  States  
Floating-Domain Integrated GaN Driver Techniques for DC-DC Converters: A Review Journal article
Xuchu Mu, Guangshu Zhao, Anyang Zhao, Yang Jiang, Man-Kay Law, Makoto Takamiya, Pui-In Mak, Rui P. Martins. Floating-Domain Integrated GaN Driver Techniques for DC-DC Converters: A Review[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70, 3790-3805.
Authors:  Xuchu Mu;  Guangshu Zhao;  Anyang Zhao;  Yang Jiang;  Man-Kay Law; et al.
Favorite | TC[WOS]:4 TC[Scopus]:4  IF:5.2/4.5 | Submit date：2023/07/14
Adaptive Dead Time  Bootstrapping  Buck Converter  Emi  Gan  Gate Driver  Integration  Reliability  
A 218 GOPS neural network accelerator based on a novel cost-efficient surrogate gradient scheme for pattern classification Journal article
Siddique, Ali, Iqbal, Muhammad Azhar, Aleem, Muhammad, Islam, Muhammad Arshad. A 218 GOPS neural network accelerator based on a novel cost-efficient surrogate gradient scheme for pattern classification[J]. Microprocessors and Microsystems, 2023, 99, 104831.
Authors:  Siddique, Ali;  Iqbal, Muhammad Azhar;  Aleem, Muhammad;  Islam, Muhammad Arshad
Favorite | TC[WOS]:2 TC[Scopus]:3  IF:1.9/2.0 | Submit date：2023/07/20
Activation Function  Artificial Neural Networks (Anns)  Deep Learning (Dl)  Dying Relu  Field Programmable Gate Arrays (Fpgas)  Giga OPerations Per Second (Gops)  Surrogate Gradient  
An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications Journal article
Zhao, Zhongyu, Cao, Rujian, Un, Ka Fai, Yu, Wei Han, Mak, Pui In, Martins, Rui P.. An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(1), 281-285.
Authors:  Zhao, Zhongyu;  Cao, Rujian;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In; et al.
Favorite | TC[WOS]:8 TC[Scopus]:12  IF:4.0/3.7 | Submit date：2022/08/08
Transformers  Energy Efficiency  Broadcasting  Convolutional Neural Networks  Integrated Circuit Modeling  Field Programmable Gate Arrays  Random Access Memory  Dataflow  Digital Accelerator  Energy-efficient  Field-programmable Gate Array (Fpga)  Energy Efficiency  Image Recognition  Transformer