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L: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs Journal article
Wang, Bo, Law, Man Kay, Schneider, Jens. L: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs[J]. IEEE Transactions on Signal Processing, 2023, 71, 3229-3241.
Authors:  Wang, Bo;  Law, Man Kay;  Schneider, Jens
Favorite | TC[WOS]:2 TC[Scopus]:1  IF:4.6/5.2 | Submit date：2024/02/22
Analog-to-digital Data Converter  Digital Linear Filter  Frequency Notch  Incremental Delta-sigma Adc  l  Reconstruction Filter  Thermal Noise Penalty  
Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs Journal article
Jiang, D., Sin, S. W., Qi, L., Wang, G., Martins, R. P.. Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs[J]. IEEE Open Journal of the Solid-State Circuits Society, 2021, 129-139.
Authors:  Jiang, D.;  Sin, S. W.;  Qi, L.;  Wang, G.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
ADC  analog-to-digital converter  DAC  digital-to-analog-converter  hybrid ADC  incremental ADC (I-ADC)  delta-sigma modulator  time-Interleaving  extrapolating  noise shaping  successive approximation register  SAR.  
Near-Optimal Decoding of Incremental Delta-Sigma ADC Output Journal article
Wang,Bo, Law,Man Kay, Belhaouari,Samir Brahim, Bermak,Amine. Near-Optimal Decoding of Incremental Delta-Sigma ADC Output[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 67(11), 3670-3680.
Authors:  Wang,Bo;  Law,Man Kay;  Belhaouari,Samir Brahim;  Bermak,Amine
Favorite | TC[WOS]:8 TC[Scopus]:8  IF:5.2/4.5 | Submit date：2021/03/11
Decimation Filter  Delta-sigma Modulator  Idc  Incremental Adc  Noise Penalty Factor  Optimal Filter  Reconstruction Filter  Thermal Noise Averaging  
A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin, S. W., U, S.P., Maloberti, F., Martins, R. P.. A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits (Invited Special Issue of VLSI), 2019, 1161-1172.
Authors:  Wang, B.;  Sin, S. W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |   IF:4.6/5.6 | Submit date：2022/01/25
Analog-to-digital Converter  Iadc  Incremental Adc  Sigma-delta  Linear  Exponential  Accumulation  Two-phase  Multi-bit  Mismatch Error  Dynamic Element Matching (Dem)  Data Weighting Average (Dwa)  High Linearity  Notch  
A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin,Sai Weng, Seng-Pan,S. P.U., Maloberti,Franco, Martins,Rui P.. A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2019, 54(4), 1161-1172.
Authors:  ; et al.
Favorite | TC[WOS]:44 TC[Scopus]:55  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Data Weighting Average  Dynamic Element Matching (Dem)  High Linearity  Incremental Adc (iAdc)  Linear-exponential Accumulation  Mismatch Error  Multi-bit  Notch  Sigma Delta  Two Phase  
A 2.2μW 15b incremental delta-sigma ADC with output-driven input segmentation Conference paper
Wang B., Law M.K., Mohamad S., Bermak A.. A 2.2μW 15b incremental delta-sigma ADC with output-driven input segmentation[C], 2016, 7-8.
Authors:  Wang B.;  Law M.K.;  Mohamad S.;  Bermak A.
Favorite | TC[WOS]:1 TC[Scopus]:2 | Submit date：2019/02/14
Dual-feedback Σs Modulator  Incremental Delta-sigma Adc  Integrator Multiplexing  Low Power Adc