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22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer Conference paper
Cao, Yuefeng, Zhang, Minglei, Zhu, Yan, Martins, R. P., Chan, Chi Hang. 22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 388-390.
Authors:  Cao, Yuefeng;  Zhang, Minglei;  Zhu, Yan;  Martins, R. P.;  Chan, Chi Hang
Favorite | TC[Scopus]:1 | Submit date：2024/05/16
Radio Frequency  Power Measurement  Measurement Uncertainty  Linearity  Hardware  Energy Efficiency  Calibration  
An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration Journal article
Zhang, Hongshuai, Zhu, Yan, Chan, Chi Hang, Martins, Rui P.. An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57(5), 1480-1491.
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite | TC[WOS]:8 TC[Scopus]:10  IF:4.6/5.6 | Submit date：2022/05/13
Amplifier Linearity Enhancement  Analog-to-digital Converter (Adc)  Background Offset Calibration  Digital Reconstruction Filter  Dwa  Energy And Area Efficient  Inherent Gain Error Tolerant  Inter-stage Gain Error  Noise Shaping (Ns)  Oversampling  Partial Interleaving  Pipelined Successive Approximation (Sar)  Quantization Leakage Error  
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier Journal article
Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi Hang Chan, Jan Craninckx, Rui P. Martins. A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier[J]. IEEE Journal of Solid-State Circuits, 2021.
Authors:  Zihao Zheng;  Lai Wei;  Jorge Lagos;  Ewout Martens;  Yan Zhu; et al.
Favorite | TC[WOS]:8 TC[Scopus]:9  IF:4.6/5.6 | Submit date：2021/09/20
Analog-to-digital Conversion  Calibration  Calibration  Dynamic Amplifier (Da)  Hardware  Linearity  Linearization Technique  Pipeline Processing  Pipelined Analog-to-digital Converter (Adc).  Quantization (Signal)  Signal Resolution  System-on-chip  
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC Journal article
Jianwei Liu, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins. Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(7), 2603-2607.
Authors:  Jianwei Liu;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U; et al.
Favorite | TC[WOS]:14 TC[Scopus]:18 | Submit date：2019/02/14
Background Linearity Calibration  Splitdigital- To-analog Converter (Dac)  Successive Approximation Register (Sar) Adc  Uniform Quantization Theory (Uqt)  
Histogram-based ratio mismatch calibration for bridge-DAC in 12-bit 120 MS/s SAR ADC Journal article
Yan Zhu, Chi-Hang Chan, Si-Seng Wong, U Seng-Pan, Rui Paulo Martins. Histogram-based ratio mismatch calibration for bridge-DAC in 12-bit 120 MS/s SAR ADC[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(3), 1203-1207.
Authors:  Yan Zhu;  Chi-Hang Chan;  Si-Seng Wong;  U Seng-Pan;  Rui Paulo Martins
Favorite | TC[WOS]:29 TC[Scopus]:32 | Submit date：2019/02/11
Bridge Dac  Linearity Calibration  Sar Adc  
Split-SAR ADCs: Improved linearity with power and speed optimization Journal article
Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti. Split-SAR ADCs: Improved linearity with power and speed optimization[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22(2), 372-383.
Authors:  Yan Zhu;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U; et al.
Favorite | TC[WOS]:44 TC[Scopus]:56 | Submit date：2018/10/30
Linearity Analysis  Linearity Calibration  Sar Adcs  Split Dac  Vcm-based Switching