UM

Browse/Search Results:  1-10 of 21 Help

Selected(0)Clear Items/Page:    Sort:
Robust allocation of distributed energy storage systems considering locational frequency security Journal article
Rushuai Han, Qinran Hu, Hongcai Zhang, Yi Ge, Xiangjun Quan, Zaijun Wu. Robust allocation of distributed energy storage systems considering locational frequency security[J]. International Journal of Electrical Power & Energy Systems, 2024, 157, 109903.
Authors:  Rushuai Han;  Qinran Hu;  Hongcai Zhang;  Yi Ge;  Xiangjun Quan; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:5.0/4.6 | Submit date:2024/04/24
Locational Frequency Security  Distributed Energy Storage Systems  Fast Frequency Support  Constraint Linearization  Robust Allocation  
A 52.5-dB 2x Time-Interleaved 2.8-GS/s SAR ADC with 5-Bit/Cycle Time-Domain Quantization and a Compact Signal DAC Journal article
Zhao, Hongzhi, Zhang, Minglei, Zhu,Yan, Martins, R. P., Chan,Chi Hang. A 52.5-dB 2x Time-Interleaved 2.8-GS/s SAR ADC with 5-Bit/Cycle Time-Domain Quantization and a Compact Signal DAC[J]. IEEE Journal of Solid-State Circuits, 2023, 58(12), 3586-3597.
Authors:  Zhao, Hongzhi;  Zhang, Minglei;  Zhu,Yan;  Martins, R. P.;  Chan,Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.6/5.6 | Submit date:2023/08/29
Analog-to-digital Converter (Adc)  Multi-bit/cycle Successive-approximation Register (Sar) Adc  Time-domain Quantization  Voltage-to-time (V2t) Buffer  Linearization  
A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors Conference paper
Zhang, Minglei, Cao, Yuefeng, Zhu, Yan, Chan, Chi-Hang, Martins, R. P.. A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors[C]:Institute of Electrical and Electronics Engineers Inc., 2023.
Authors:  Zhang, Minglei;  Cao, Yuefeng;  Zhu, Yan;  Chan, Chi-Hang;  Martins, R. P.
Favorite | TC[Scopus]:2 | Submit date:2023/07/12
Dynamic Amplifier  Residue Amplifier  Pipelined-sar Adc  Linearization Technique  Bypass Capacitor  
Chance-constrained DC Optimal Power Flow with Non-Gaussian Distributed Uncertainties Conference paper
Ge Chen, Hongcai Zhang, Yonghua Song. Chance-constrained DC Optimal Power Flow with Non-Gaussian Distributed Uncertainties[C], 2022.
Authors:  Ge Chen;  Hongcai Zhang;  Yonghua Song
Favorite | TC[Scopus]:3 | Submit date:2023/01/30
Dc Optimal Power Flow  Chance-constrained Programming  Non-gaussian Uncertainties  Gaussian Mixture Model  Linearization  
A SPATIALLY SIXTH-ORDER HYBRID L1-CCD METHOD FOR SOLVING TIME FRACTIONAL SCHRÖDINGER EQUATIONS Journal article
Zhang,Chun Hua, Jin,Jun Wei, Sun,Hai Wei, Sheng,Qin. A SPATIALLY SIXTH-ORDER HYBRID L1-CCD METHOD FOR SOLVING TIME FRACTIONAL SCHRÖDINGER EQUATIONS[J]. Applications of Mathematics, 2021, 66(2), 213–232.
Authors:  Zhang,Chun Hua;  Jin,Jun Wei;  Sun,Hai Wei;  Sheng,Qin
Favorite | TC[WOS]:3 TC[Scopus]:5  IF:0.6/0.6 | Submit date:2021/03/09
Nonlinear Time Fractional Schrödinger Equations  L1 Formula  Hybrid Compact Difference Method  Linearization  Unconditional Stability  
An 800 MHz-to-3.3 GHz 20-MHz Channel Bandwidth WPD CMOS Power Amplifier for Multiband Uplink Radio Transceivers Journal article
Mariappan, Selvakumar, Rajendran, Jagadheswaran, Ramiah, Harikrishnan, Mak, Pui In, Yin, Jun, Martins, Rui P.. An 800 MHz-to-3.3 GHz 20-MHz Channel Bandwidth WPD CMOS Power Amplifier for Multiband Uplink Radio Transceivers[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 68(4), 1178-1182.
Authors:  Mariappan, Selvakumar;  Rajendran, Jagadheswaran;  Ramiah, Harikrishnan;  Mak, Pui In;  Yin, Jun; et al.
Favorite | TC[WOS]:4 TC[Scopus]:5  IF:4.0/3.7 | Submit date:2021/09/20
Cmos  Evm  Linearization  Lte  Power Amplifier (Pa)  Pre-distorter  
A SPATIALLY SIXTH-ORDER HYBRID L1-CCD METHOD FOR SOLVING TIME FRACTIONAL SCHRÖDINGER EQUATIONS Journal article
Zhang,Chun Hua, Jin,Jun Wei, Sun,Hai Wei, Sheng,Qin. A SPATIALLY SIXTH-ORDER HYBRID L1-CCD METHOD FOR SOLVING TIME FRACTIONAL SCHRÖDINGER EQUATIONS[J]. Applications of Mathematics, 2021, 66(2), 213-232.
Authors:  Zhang,Chun Hua;  Jin,Jun Wei;  Sun,Hai Wei;  Sheng,Qin
Favorite | TC[WOS]:3 TC[Scopus]:5  IF:0.6/0.6 | Submit date:2022/07/25
Nonlinear Time Fractional Schrödinger Equations  L1 Formula  Hybrid Compact Difference Method  Linearization  Unconditional Stability  
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier Journal article
Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi Hang Chan, Jan Craninckx, Rui P. Martins. A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier[J]. IEEE Journal of Solid-State Circuits, 2021.
Authors:  Zihao Zheng;  Lai Wei;  Jorge Lagos;  Ewout Martens;  Yan Zhu; et al.
Favorite | TC[WOS]:8 TC[Scopus]:9  IF:4.6/5.6 | Submit date:2021/09/20
Analog-to-digital Conversion  Calibration  Calibration  Dynamic Amplifier (Da)  Hardware  Linearity  Linearization Technique  Pipeline Processing  Pipelined Analog-to-digital Converter (Adc).  Quantization (Signal)  Signal Resolution  System-on-chip  
Single Bus Data-driven Power Estimation Based on Modified Linear Power Flow Model Conference paper
Xing, Zheng, Gong, Jian Hua, Lao, Keng Weng, Dai, Ning Yi. Single Bus Data-driven Power Estimation Based on Modified Linear Power Flow Model[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2021, 755-758.
Authors:  Xing, Zheng;  Gong, Jian Hua;  Lao, Keng Weng;  Dai, Ning Yi
Favorite | TC[Scopus]:4 | Submit date:2022/05/13
Power Estimation  Linearization  Data-driven  Power Flow Model  
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
Qi,Liang, Jain,Ankesh, Jiang,Dongyang, Sin,Sai Weng, Martins,Rui P., Ortmanns,Maurits. A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance[J]. IEEE Journal of Solid-State Circuits, 2019, 55(2), 344-355.
Authors:  Qi,Liang;  Jain,Ankesh;  Jiang,Dongyang;  Sin,Sai Weng;  Martins,Rui P.; et al.
Favorite | TC[WOS]:54 TC[Scopus]:48  IF:4.6/5.6 | Submit date:2021/03/09
Analog-to-digital Converter (Adc)  Continuous Time (Ct)  Digital-to-analog Converter (Dac) Linearization  Excess Loop Delay (Eld) Compensation  Filter  Finite-impulse Response (Fir)  Multibit Quantization  Noise Coupling (Nc)  Sturdy Multistage Noise-shaping (Smash)  Successive-approximation Register (Sar)