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A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity Journal article
Wu, Hao, Chen, Yong, Yuan, Yiyang, Yue, Jinshan, Wang, Xinghua, Li, Xiaoran, Zhang, Feng. A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Wu, Hao;  Chen, Yong;  Yuan, Yiyang;  Yue, Jinshan;  Wang, Xinghua; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/07/04
Accuracy  Artificial Intelligence  Artificial Intelligence (Ai)  Circuits  Cmos  Computing-in-memory (Cim)  Energy Efficiency  Energy Efficiency  Look-up Table (Lut)  Multiply-accumulation (Mac)  Neural Network (Nn)  Power Demand  Radix16  Table Lookup  Throughput  Unstructured Sparsity  Winograd Convolution  
Reconfigurable mismatch-free time-interleaved bandpass sigma-delta modulator for wireless communications Journal article
Dongyang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti. Reconfigurable mismatch-free time-interleaved bandpass sigma-delta modulator for wireless communications[J]. ELECTRONICS LETTERS, 2017, 53(7), 506–508.
Authors:  Dongyang Jiang;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite | TC[WOS]:2 TC[Scopus]:3  IF:0.7/0.9 | Submit date：2018/10/30
Sigma-delta Modulation  Modulators  Software Radio  Radio Receivers  Circuit Simulation  Band-pass Filters  Table Lookup  Reconfigurable Mismatch-free Time-interleaved Bandpass Sigma-delta Modulator  Wireless Communications  Control Parameters  Look-up Table  Path Numbers  Path Sampling Frequencies  Tuning Coefficients  Design Reconfigurability  Multiband Receiver  Software Defined Radio Systems  Behavioural Simulations