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A Two-phase Multi-bit Incremental ADC with Variable Loop Order Journal article
Chen,Kaiquan, Wang,Biao, Liu,Yan, Ye,Fan, Sin,Sai Weng, Wang,Guoxing, Lian,Yong, Qi,Liang. A Two-phase Multi-bit Incremental ADC with Variable Loop Order[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(8), 2724-2728.
Authors:  Chen,Kaiquan;  Wang,Biao;  Liu,Yan;  Ye,Fan;  Sin,Sai Weng; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2023/08/03
Circuits And Systems  Variable Loop Order  Multi-bit Quantizer  Dwa Effectiveness  Noise Penalty  
A high resolution multi-bit incremental converter insensitive to DAC mismatch error Conference paper
Biao Wang, Sai-Weng Sin, Seng-Pan U, R. P. Martins. A high resolution multi-bit incremental converter insensitive to DAC mismatch error[C], 2016.
Authors:  Biao Wang;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite | TC[WOS]:2 TC[Scopus]:8 | Submit date：2019/02/11
High Resolution  Incremental Converter  Multi-bit Quantizer  Insensitive To Dac Mismatch