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A 3.57-mW 2.88-GHz Multi-Phase Injection-Locked Ring-VCO with a 200-kHz 1/f3 Phase Noise Corner Journal article
Fan, Chao, Zhao, Ya, Zhang, Yanlong, Yin, Jun, Geng, Li, Mak, Pui In. A 3.57-mW 2.88-GHz Multi-Phase Injection-Locked Ring-VCO with a 200-kHz 1/f3 Phase Noise Corner[J]. IEEE Transactions on Circuits and Systems II - Express Briefs, 2022, 70(3), 865-869.
Authors:  Fan, Chao;  Zhao, Ya;  Zhang, Yanlong;  Yin, Jun;  Geng, Li; et al.
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:4.0/3.7 | Submit date：2023/01/30
Cmos  Ring Voltage-controlled Oscillator (Rvco)  Phase Noise  Flicker Noise  1/f3 Phase Noise Corner  Inherent Low-frequency Output  Multi-phase Injection Locking (Mpil)  Clock Generation  
Noise-Regularized Advantage Value for Multi-Agent Reinforcement Learning Journal article
Wang, Siying, Chen, Wenyu, Hu, Jian, Hu, Siyue, Huang, Liwei. Noise-Regularized Advantage Value for Multi-Agent Reinforcement Learning[J]. Mathematics, 2022, 10(15), 2728.
Authors:  Wang, Siying;  Chen, Wenyu;  Hu, Jian;  Hu, Siyue;  Huang, Liwei
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:2.3/2.2 | Submit date：2023/01/30
Advantage Function  Exploration  Multi-agent Reinforcement Learning  Noise Injection  Proximal Policy Optimization  
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop Journal article
Liu, Yueduo, Bao, Rongxin, Zhu, Zihao, Yang, Shiheng, Zhou, Xiong, Li, Qiang, Yin, Jun, Mak, Pui In. Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(2), 495-505.
Authors:  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2022/03/04
Voltage-controlled Oscillators  Jitter  Clocks  Phase Noise (Pn)  Topology  Performance Evaluation  Delays  Figure Of Merit (Fom)  Injection-locked Clock Multiplier (Ilcm)  Multiplying Delay-locked Loop (Mdll)  Power  Ring Voltage-controlled Oscillator (Rvco)  
A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer with Integrated Transformer-Based Gate Inductor and IM2 Injection Technique Journal article
Vitee,Nandini, Ramiah,Harikrishnan, Mak,Pui In, Yin,Jun, Martins,Rui P.. A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer with Integrated Transformer-Based Gate Inductor and IM2 Injection Technique[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020, 28(3), 700-713.
Authors:  Vitee,Nandini;  Ramiah,Harikrishnan;  Mak,Pui In;  Yin,Jun;  Martins,Rui P.
Favorite | TC[WOS]:15 TC[Scopus]:25  IF:2.8/2.8 | Submit date：2021/03/04
Balun-low-noise Amplifier (Lna) Mixer  Cmos  High Linearity  Inductively Source Degeneration Transconductor  Low-power  Second-order Intermodulation (Im2) Injection  Third-order Input Intercept Point (Iip3)  Volterra Series  
A 0.0056-mm² -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs Journal article
Yang, S., Yin, J., Mak, P. I., Martins, R. P.. A 0.0056-mm² -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 88-98.
Authors:  Yang, S.;  Yin, J.;  Mak, P. I.;  Martins, R. P.
Favorite | TC[WOS]:27 TC[Scopus]:28  IF:4.6/5.6 | Submit date：2022/01/24
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
Shiheng Yang, Jun Yin, Pui-In Mak, Rui P. Martins. A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs[J]. IEEE Journal of Solid-State Circuits, 2019, 54(1), 88-98.
Authors:  Shiheng Yang;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:27 TC[Scopus]:28  IF:4.6/5.6 | Submit date：2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter