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An 18-Gb/s fully integrated optical receiver with adaptive cascaded equalizer Journal article
Pan Q., Wang Y., Lu Y., Yue C.P.. An 18-Gb/s fully integrated optical receiver with adaptive cascaded equalizer[J]. IEEE Journal on Selected Topics in Quantum Electronics, 2016, 22(6).
Authors:  Pan Q.;  Wang Y.;  Lu Y.;  Yue C.P.
Favorite | TC[WOS]:24 TC[Scopus]:29 | Submit date：2019/02/14
Adaptive Equalizer  Continuous-time Linear Equalizer (Ctle)  Dc Offset Cancellation  Inverter-based Cascode Transimpedance Amplifier  Limiting Amplifier (La)  Low Dropout Regulator  Optical Receivers  Optoelectronic Integrated Circuits  Silicon Photodetector  
A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation Journal article
Zhu, Y., Chan, C.H., Sin, S. W., U, S.P., Martins, R. P., Maloberti, F.. A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation[J]. IEEE Journal of Solid-State Circuits (SCI, IF=3.22), 2012, 2614-2626.
Authors:  Zhu, Y.;  Chan, C.H.;  Sin, S. W.;  U, S.P.;  Martins, R. P.; et al.
Favorite |   IF:4.6/5.6 | Submit date：2022/01/24
Analog-to-digital Converter  Adc  Pipelined-sar  Offset-cancellation  Decoupled Flip-around Mdac  Vdd-attenuator  
A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC and self-embedded offset cancellation Journal article
Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti. A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC and self-embedded offset cancellation[J]. IEEE Journal of Solid-State Circuits, 2012, 47(11), 2614-2626.
Authors:  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins; et al.
Favorite | TC[WOS]:28 TC[Scopus]:33  IF:4.6/5.6 | Submit date：2018/10/30
Decoupled Flip-around Mdac  Offset-cancellation  Pipelined-sar Adc  Vdd -attenuator