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A 4-b 7µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation Journal article
Lei, X.W., Zhu, Y., Chan, C. H., Martins, R. P.. A 4-b 7µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS,, 2019, 3365-3372.
Authors:  Lei, X.W.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/25
Bluetooth low energy (BLE)  frequency-shift keying (FSK)  low power  phase ADC.  
A 4-b 7-μ W phase domain ADC with time domain reference generation for low-power FSK/PSK Demodulation Journal article
Lei,Xuewei, Chan,Chi Hang, Zhu,Yan, Martins,Rui Paulo. A 4-b 7-μ W phase domain ADC with time domain reference generation for low-power FSK/PSK Demodulation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(9), 3365-3372.
Authors:  Lei,Xuewei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui Paulo
Favorite | TC[WOS]:0 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2021/03/09
Bluetooth Low Energy (Ble)  Frequency-shift Keying (Fsk)  Low Power  Phase Adc  
A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin, S. W., U, S.P., Maloberti, F., Martins, R. P.. A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits (Invited Special Issue of VLSI), 2019, 1161-1172.
Authors:  Wang, B.;  Sin, S. W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |   IF:4.6/5.6 | Submit date：2022/01/25
Analog-to-digital Converter  Iadc  Incremental Adc  Sigma-delta  Linear  Exponential  Accumulation  Two-phase  Multi-bit  Mismatch Error  Dynamic Element Matching (Dem)  Data Weighting Average (Dwa)  High Linearity  Notch  
A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin,Sai Weng, Seng-Pan,S. P.U., Maloberti,Franco, Martins,Rui P.. A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2019, 54(4), 1161-1172.
Authors:  Wang, B.;  Sin,Sai Weng;  Seng-Pan,S. P.U.;  Maloberti,Franco;  Martins,Rui P.
Favorite | TC[WOS]:48 TC[Scopus]:60  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Data Weighting Average  Dynamic Element Matching (Dem)  High Linearity  Incremental Adc (iAdc)  Linear-exponential Accumulation  Mismatch Error  Multi-bit  Notch  Sigma Delta  Two Phase