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A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment Journal article
Li, Haoran, Xu, Tailong, Meng, Xi, Yin, Jun, Martins, Rui P., Mak, Pui In. A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Li, Haoran;  Xu, Tailong;  Meng, Xi;  Yin, Jun;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/10/10
Fast Locking  Frequency Synthesis  Frequency-locked Loop (Fll)  Low Jitter  Millimeter-wave (Mm-wave)  Phase-locked Loop (Pll)  Reference (Ref.) Spur  Sub-sampling Phase Detector (Sspd)  Voltage-controlled Oscillator (Vco)  
A Battery-Free Crystal-Less BLE Transmitter Tag With Fully-Integrated RF Harvesting and Multitag TDD and FDD Broadcasting Journal article
Lin, Liwen, Yu, Wei Han, Shao, Haijun, Yin, Jun, Lei, Ka Meng, Martins, Rui P., Mak, Pui In. A Battery-Free Crystal-Less BLE Transmitter Tag With Fully-Integrated RF Harvesting and Multitag TDD and FDD Broadcasting[J]. IEEE Transactions on Microwave Theory and Techniques, 2024.
Authors:  Lin, Liwen;  Yu, Wei Han;  Shao, Haijun;  Yin, Jun;  Lei, Ka Meng; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.1/4.2 | Submit date：2024/10/10
Battery  Bluetooth Low Energy (Ble)  Crystal (Xtal)  Frequency Retaining Technique  Frequency-division Duplex (Fdd)  Over-the-air (Ota)  Rf Reference Phase-locked Loop (Pll)  Time-division Duplex (Tdd)  Trifilar Rf Harvester  Vdd-insensitive Voltage Control Oscillator And Power Amplifier (Vco-pa)  
Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal–oxide–semiconductor Journal article
Yang, Chaowei, Chen, Yong, Cheng, Kai, Stefano, Crovetti Paolo, Martins, Rui P., Mak, Pui In. Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal–oxide–semiconductor[J]. International Journal of Circuit Theory and Applications, 2024.
Authors:  Yang, Chaowei;  Chen, Yong;  Cheng, Kai;  Stefano, Crovetti Paolo;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:1.8/1.7 | Submit date：2024/08/05
Clock And Data Recovery (Cdr)  Cmos Figure-of-merit (Fom)  Figure-of-merit With Tuning And Area (Fomta)  Figure-of-merit With Tuning Range (Fomt)  Flicker (1/f)  Noise Noise Transfer Phase Noise (Pn)  Phase-locked Loop (Pll)  Quality Factor Switched-capacitor Array (Sca)  Thermal Noise Transformer Tuning Range (Tr)  Ultra-wide-tuning-range Voltage-controlled Oscillator (Vco)  
A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM Journal article
Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Feng, Chaoping, Chen, Tianle, Zhang, Xinming, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Iizuka, Tetsuya, Chen, Yong, Mak, Pui In, Han, Zhengsheng, Li, Bo. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551.
Authors:  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Feng, Chaoping;  Chen, Tianle; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2  IF:0/0 | Submit date：2024/05/16
Double Sampling (Ds)  Figure Of Merit (Fom)  Frequency Synthesizer  Low Jitter  Low Spur  Phase Detector (Pd)  Phase-locked Loop (Pll)  Phase Noise (Pn)  Reference Sampling (Rs)  Subsampling (Ss)  Phase Locked Loops  Type-i  
A 21.8-41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller Journal article
Chen, Wen, Shu, Yiyang, Yin, Jun, Mak, Pui In, Gao, Xiang, Luo, Xun. A 21.8-41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller[J]. IEEE Transactions on Microwave Theory and Techniques, 2024.
Authors:  Chen, Wen;  Shu, Yiyang;  Yin, Jun;  Mak, Pui In;  Gao, Xiang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.1/4.2 | Submit date：2024/05/16
Detectors  Fast Locking  Frequency Locked Loops  Jitter  Jitter  Millimeter Wave (mm-Wave)  Phase Locked Loops  Phase Noise  Subsampling Phase-locked Loop (Sspll)  Voltage-controlled Oscillators  Wideband  Wideband  
A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM Conference paper
Shen, Xinyu, Zhang, Zhao, Li, Guike, Chen, Yong, Qi, Nan, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM[C]:IEEE, 2023, 257-260.
Authors:  Shen, Xinyu;  Zhang, Zhao;  Li, Guike;  Chen, Yong;  Qi, Nan; et al.
Favorite | TC[WOS]:0 TC[Scopus]:1 | Submit date：2024/02/22
Cmos.  Fractional-n(Fn)  Loop Bandwidth Tracking  Ring Sampling Phase-locked Loop (Rspll)  Wideband  
A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS Journal article
Yang,Jian, Pan,Quan, Yin,Jun, Mak,Pui In. A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS[J]. IEEE Transactions on Microwave Theory and Techniques, 2023, 71(8), 3596 - 3604.
Authors:  Yang,Jian;  Pan,Quan;  Yin,Jun;  Mak,Pui In
Favorite | TC[WOS]:4 TC[Scopus]:4  IF:4.1/4.2 | Submit date：2023/08/03
Charge Pump (Cp)  Clock Generator  Delay-locked Loop (Dll)  Locking Range  Multiphase Clock  Phase Accuracy  
Ring-VCO-based Phase-Locked Loops for Clock Generation – Design Considerations and State-of-the-Art Journal article
Shiheng Yang, Jun Yin, Yueduo Liu, Rongxin Bao, Zihao Zhu, Jiahui Lin, Qiang Li, Pui-In Mak, Rui P. Martins. Ring-VCO-based Phase-Locked Loops for Clock Generation – Design Considerations and State-of-the-Art[J]. Chip, 2023, 2(2), 1-10.
Authors:  Shiheng Yang;  Jun Yin;  Yueduo Liu;  Rongxin Bao;  Zihao Zhu; et al.
Favorite | TC[WOS]:1 TC[Scopus]:3 | Submit date：2023/08/19
Clock Generation, Ic Design, Phase-locked Loop (Pll), Frequency Synthesizer  
A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur Journal article
Huang, Yunbo, Chen, Yong, Zhao, Bo, Mak, Pui In, Martins, Rui P.. A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 70(4), 1463-1475.
Authors:  Huang, Yunbo;  Chen, Yong;  Zhao, Bo;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:6 TC[Scopus]:11  IF:5.2/4.5 | Submit date：2023/05/02
Cmos  Type-i Sampling Phase-locked Loop (S-pll)  Voltage-controlled Oscillator (Vco)  Reference (Ref) Feedthrough Suppression  Figure-of-merit (Fom)  Phase-detection Gain (Kpd)  Sampling Phase Detector (S-pd)  
Universal Stability Criterion for Type-I Sampling Phase-Locked Loops Journal article
Huang, Yunbo, Chen, Yong, Mak, Pui In, Martins, Rui P.. Universal Stability Criterion for Type-I Sampling Phase-Locked Loops[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(4), 1351-1355.
Authors:  Huang, Yunbo;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:3 TC[Scopus]:3  IF:4.0/3.7 | Submit date：2023/05/02
Given Phase Margin (Pm)  Linear Time-variant (Ltv) Mode  Sampling Phase-locked Loop (S-pll)  Sub-sampling Pll (ss-Pll)  Type-i  Voltage-controlled Oscillator (Vco)