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A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW2 Pipeline and Adaptive-Resolution Quantization Journal article
Li, Jixuan, Li, Ke, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW2 Pipeline and Adaptive-Resolution Quantization[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
Authors:  Li, Jixuan;  Li, Ke;  Un, Ka Fai;  Yu, Wei Han;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/12/26
Convolutional Neural Network (Cnn)  Digital Signal Processing (Dsp)  Field-programmable Gate Array (Fpga)  Processing Unit (Pe) Utilization  Residual Block