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Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC Journal article
Li, Cheng, Chan, Chi-Hang, Zhu, Yan, Martins, Rui P.. Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66(1), 82-93.
Authors:  Li, Cheng;  Chan, Chi-Hang;  Zhu, Yan;  Martins, Rui P.
Favorite | TC[WOS]:11 TC[Scopus]:14  IF:5.2/4.5 | Submit date：2019/01/17
Reference Error  Reference Buffer  Successive-approximation-register (Sar)  Analog-to-digital Converter (Adc)  Reference Ripple  
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration Journal article
Chan, Chi-Hang, Zhu, Yan, Li, Cheng, Zhang, Wai-Hong, Ho, Iok-Meng, Wei, Lai, Seng-Pan, U., Martins, Rui Paulo. 60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017, 52(10), 2576-2588.
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Li, Cheng;  Zhang, Wai-Hong;  Ho, Iok-Meng; et al.
Favorite | TC[WOS]:39 TC[Scopus]:47  IF:4.6/5.6 | Submit date：2018/10/30
Reference Buffer  Reference Error Calibration  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Threshold Reconfigurable Comparator  
Single-trial detection of error-related potential by one-unit SOBI-R in SSVEP-based BCI Conference paper
da Cruz J.N., Wang Z., Wong C.M., Wan F.. Single-trial detection of error-related potential by one-unit SOBI-R in SSVEP-based BCI[C], 2014, 524-532.
Authors:  da Cruz J.N.;  Wang Z.;  Wong C.M.;  Wan F.
Favorite | TC[WOS]:3 TC[Scopus]:3 | Submit date：2018/12/24
Brain-computer Interface (Bci)  Error-related Potentials (Errp)  One-unit Second-order Blind Identification With Reference (Sobi-r)  Steady-state Visual Evoked Potentials (Ssvep)