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A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM Journal article
Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Feng, Chaoping, Chen, Tianle, Zhang, Xinming, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Iizuka, Tetsuya, Chen, Yong, Mak, Pui In, Han, Zhengsheng, Li, Bo. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551.
Authors:  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Feng, Chaoping;  Chen, Tianle; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2  IF:0/0 | Submit date：2024/05/16
Double Sampling (Ds)  Figure Of Merit (Fom)  Frequency Synthesizer  Low Jitter  Low Spur  Phase Detector (Pd)  Phase-locked Loop (Pll)  Phase Noise (Pn)  Reference Sampling (Rs)  Subsampling (Ss)  Phase Locked Loops  Type-i  
Power-Efficient RF and mm-Wave VCOs/PLL Book chapter
出自: Analog Circuits and Signal Processing, Switzerland:Springer, 2023, 页码:51-89
Authors:  Hao Guo;  Zunsong Yang;  Chee Cheow Lim;  Harikrishnan Ramiah;  Yatao Peng; et al.
Favorite | TC[Scopus]:0 | Submit date：2023/08/03
Harmonic Tuning  Inverse Class-f  Jitter  Millimeter Wave (mm-Wave)  Mode-switching  Phase Noise  Phase-locked Loop (Pll)  Reference Spur  Subsampling  Voltage-controlled Oscillator (Vco)  
A 6-to-7.5-GHz 54-fsrmsJitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction Journal article
Xu, Tailong, Zhong, Shenke, Yin, Jun, Mak, Pui In, Martins, Rui P.. A 6-to-7.5-GHz 54-fsrmsJitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(12), 4774-4786.
Authors:  Xu, Tailong;  Zhong, Shenke;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:6 TC[Scopus]:8  IF:5.2/4.5 | Submit date：2023/01/30
Gain-boosting  Low Jitter  Low Phase Noise  Phase-locked Loop (Pll)  Reference Spur  Reference-sampling Phase Detector (Rspd)  Sampling Phase Detector (Spd)  Sub-sampling Phase Detector (Sspd)  Switched-capacitor Voltage Multiplier  
A -40∼125∘C 0.4μA Low Noise Bandgap Voltage Reference with 0.8mA Load Driving Capability Using Shared Feedback Resistors Journal article
Zhang, Zhaobo, Zhan, Chenchang, Wang, Lidan, Law, Man Kay. A -40∼125∘C 0.4μA Low Noise Bandgap Voltage Reference with 0.8mA Load Driving Capability Using Shared Feedback Resistors[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 69(10), 4033-4037.
Authors:  Zhang, Zhaobo;  Zhan, Chenchang;  Wang, Lidan;  Law, Man Kay
Favorite | TC[WOS]:14 TC[Scopus]:17  IF:4.0/3.7 | Submit date：2022/08/05
Bandgap Reference (Bgr)  Capacitors  Codes  Low Dropout Regulator (Ldo)  Low Noise  Low Power  Low-cost Internet Of Things (Iot)  Power Supplies  Resistors  Temperature Measurement  Thermal Stability  Two Wafers  Voltage  
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM Journal article
Yang, Zunsong, Chen, Yong, Yuan, Jia, Mak, Pui In, Martins, Rui P.. A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 30(2), 238-242.
Authors:  Yang, Zunsong;  Chen, Yong;  Yuan, Jia;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:20 TC[Scopus]:21  IF:2.8/2.8 | Submit date：2022/03/04
Binary Frequency Shift Keying (Bfsk)  Frequency-locked Loop (Fll)  Integer-n  Phase Detector (Pd)  Phase Noise (Pn)  Phase-locked Loop (Pll)  Push-pull  Reference (Ref) Spur  Sub-sampling (Ss)  Voltage-controlled Oscillator (Vco)  
A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Journal article
Zunsong Yang, Yong Chen, Pui In Mak, Rui P. Martins. A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 68(6), 2307-2316.
Authors:  Zunsong Yang;  Yong Chen;  Pui In Mak;  Rui P. Martins
Favorite | TC[WOS]:13 TC[Scopus]:15  IF:5.2/4.5 | Submit date：2021/09/20
Cmos  Current-reuse Sampling Phase Detector (Crs-pd)  Integrated Jitter  Loop Filter (Lf)  Master-slave Sampling Filter (Mssf)  Master-slave Sampling Phase Detector (Mss-pd)  Phase Noise (Pn)  Phase-locked Loop (Pll)  Reference Spur  Ring Voltage-controlled Oscillator (Vco)  Type-i  Type-ii  
A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT Journal article
Xiaofeng Yang, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins. A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(11), 3753-3763.
Authors:  Xiaofeng Yang;  Chi-Hang Chan;  Yan Zhu;  Rui Paulo Martins
Favorite | TC[WOS]:8 TC[Scopus]:8  IF:5.2/4.5 | Submit date：2021/03/04
Calibration-free  Discrete-time  Gain Tracking  Jitter  Open-loop  Phase Noise Cancellation (Pnc)  Phase-locked Loop (Pll)  Pvt  Reference Spur  Ring Voltage-controlled Oscillator (Rvco)  
A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM Journal article
Yang,Zunsong, Chen,Yong, Mak,Pui In, Martins,Rui P.. A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM[J]. IEEE Solid-State Circuits Letters, 2020, 3, 494-497.
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:18 TC[Scopus]:19 | Submit date：2021/03/09
Cmos  In-band Phase Noise (Pn)  Narrow-pulse-sampling (Nps)  Phase-locked Loop (Pll)  Reference (Ref) Spur  T-shape Switch  Type-i  Voltage-controlled Oscillator (Vco)  
A 0.18V 382µW Bluetooth Low-Energy (BLE) Receiver Front-End with 1.33nW Sleep Power for Energy-Harvesting Applications in 28nm CMOS Journal article
Haidong Yi, Wei-Han Yu, Pui-In Mak, Jun Yin, Rui P. Martins. A 0.18V 382µW Bluetooth Low-Energy (BLE) Receiver Front-End with 1.33nW Sleep Power for Energy-Harvesting Applications in 28nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2018, 53(6), 1618 - 1627.
Authors:  Haidong Yi;  Wei-Han Yu;  Pui-In Mak;  Jun Yin;  Rui P. Martins
Favorite | TC[WOS]:53 TC[Scopus]:60  IF:4.6/5.6 | Submit date：2019/03/12
Bandgap Reference (Bgr)  Bluetooth Low Energy (Ble)  Charge Pump (Cp)  Class-d Voltage-controlled Oscillator (Vco)  Cmos  Energy Harvesting  Low-noise Amplifier (Lna)  Micropower Manager (Μpm)  Power-gating  Receiver (Rx)  Ultra-low Power (Ulp)  Ultra-low Voltage (Ulv)  
A 0.18-V 382-μ W Bluetooth Low-Energy Receiver Front-End with 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS Journal article
Haidong Yi, Wei-Han Yu, Pui-In Mak, Jun Yin, Rui P. Martins. A 0.18-V 382-μ W Bluetooth Low-Energy Receiver Front-End with 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2018, 53(6), 1618-1627.
Authors:  Haidong Yi;  Wei-Han Yu;  Pui-In Mak;  Jun Yin;  Rui P. Martins
Favorite | TC[WOS]:53 TC[Scopus]:60 | Submit date：2019/02/11
Bandgap Reference (Bgr)  Bluetooth Low Energy (Ble)  Charge Pump (Cp)  Class-d Voltage-controlled Oscillator (Vco)  Cmos  Energy Harvesting  Low-noise Amplifier (Lna)  Micropower Manager (Μpm)  Power-gating  Receiver (Rx)  Ultra-low Power (Ulp)  Ultra-low Voltage (Ulv)