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A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier Journal article
Jiang,Wenning, Chen,Chixiao, Liu,Qi, Liu,Ming, Zhu,Yan, Chan,Chi Hang, Xu,Hao, Martins,Rui P.. A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier[J]. IEEE Journal of Solid-State Circuits, 2023, 58(10), 2709 - 2721.
Authors:  Jiang,Wenning;  Chen,Chixiao;  Liu,Qi;  Liu,Ming;  Zhu,Yan; et al.
Favorite | TC[WOS]:5 TC[Scopus]:5  IF:4.6/5.6 | Submit date：2023/08/03
Adaptive Bias  Analog-to-digital Converter (Adc)  Floating Inverter Amplifier (Fia)  Pipelined-successive-approximation-register (Sar) Adc  Reference Ripple Cancellation (Rrc)  Reference Ripple Neutralization (Rrn)  
Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC Journal article
Li, Cheng, Chan, Chi-Hang, Zhu, Yan, Martins, Rui P.. Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66(1), 82-93.
Authors:  Li, Cheng;  Chan, Chi-Hang;  Zhu, Yan;  Martins, Rui P.
Favorite | TC[WOS]:11 TC[Scopus]:14  IF:5.2/4.5 | Submit date：2019/01/17
Reference Error  Reference Buffer  Successive-approximation-register (Sar)  Analog-to-digital Converter (Adc)  Reference Ripple