English | 繁體

Search in the results

UM

Browse/Search Results:  1-10 of 30 Help

Selected(0)Clear Items/Page:    Sort:
A 12-/13.56-MHz Crystal Oscillator with Binary-Search-Assisted Two-Step Injection Achieving 5.0-nJ Startup Energy and 45.8-μs Startup Time Journal article
Li, Haihua, Lei, Ka Meng, Martins, Rui P., Mak, Pui In. A 12-/13.56-MHz Crystal Oscillator with Binary-Search-Assisted Two-Step Injection Achieving 5.0-nJ Startup Energy and 45.8-μs Startup Time[J]. IEEE Journal of Solid-State Circuits, 2024, 59(2), 464-475.
Authors:  Li, Haihua;  Lei, Ka Meng;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2024/02/22
Binary-search Algorithm  Crystal Oscillator (Xo)  Internet-of-things (Iot)  Ring Oscillator  Sandwich Capacitor  Stepwise Injection  Two-step Injection  Ultralow Power (Ulp)  
A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS Journal article
Lu, Xin, Wu, Jiangchao, Wang, Zhao, Xiang, Yifei, Liu, Liyuan, Mak, Pui In, Martins, Rui P., Law, Man Kay. A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(8), 3635 - 3639.
Authors:  Lu, Xin;  Wu, Jiangchao;  Wang, Zhao;  Xiang, Yifei;  Liu, Liyuan; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.0/3.7 | Submit date：2024/05/16
Coarse-fine Conversion  Cyclic Time-to-digital Converter (Tdc)  Delays  Gated-ring Oscillator (Gro)  Generators  Image Edge Detection  Logic Gates  Phase Domain Reset  Ring Oscillators  Signal Resolution  Switches  
A Subthreshold Operation Series-Parallel Charge Pump Incorporating Dynamic Source-Fed Oscillator for Wide-Input-Voltage Energy Harvesting Application Journal article
Kee, Yong Jack, Ramiah, Harikrishnan, Churchill, Kishore Kumar Pakkirisami, Chong, Gabriel, Mekhilef, Saad, Lai, Nai Shyan, Chen, Yong, Mak, Pui In, Martins, Rui P.. A Subthreshold Operation Series-Parallel Charge Pump Incorporating Dynamic Source-Fed Oscillator for Wide-Input-Voltage Energy Harvesting Application[J]. IEEE Access, 2023, 11, 97641-97653.
Authors:  Kee, Yong Jack;  Ramiah, Harikrishnan;  Churchill, Kishore Kumar Pakkirisami;  Chong, Gabriel;  Mekhilef, Saad; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:3.4/3.7 | Submit date：2024/02/22
Cmos  Dc-to-dc Converter  Low Power Energy Harvesting  Power Conversion Efficiency (Pce)  Reconfigurable Charge Pump (Cp)  Ring-voltage Controlled Oscillator (Rvco)  
A 0.004-mm2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS Journal article
Zhang,Chenghao, Wei,Jiangbo, Chen,Yong, Liu,Maliang, Yang,Yintang. A 0.004-mm2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2023, 58(11), 3179-3193.
Authors:  Zhang,Chenghao;  Wei,Jiangbo;  Chen,Yong;  Liu,Maliang;  Yang,Yintang
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2023/08/03
Analog-to-digital Converter (Adc)  Calibration  Cmos  Folding  Gated Ring Oscillator (Gro)  Interpolation  Pulse Generator (Pg)  Time Domain (Td)  Voltage Domain (Vd)  
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique Journal article
Wang,Lin, Chen,Yong, Yang,Chaowei, Zhao,Xiaoteng, Mak,Pui In, Maloberti,Franco, Martins,Rui P.. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(7), 2637-2650.
Authors:  Wang,Lin;  Chen,Yong;  Yang,Chaowei;  Zhao,Xiaoteng;  Mak,Pui In; et al.
Favorite | TC[WOS]:1 TC[Scopus]:4  IF:5.2/4.5 | Submit date：2023/08/03
Bang-bang Clock And Data Recovery (Bbcdr)  Wide Capture Range  Single Loop  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Deliberate Current Mismatch  Ring Oscillator (Ro)  R-2r Dac  Positive (Pnc)  Negative (Nnc) And Zero (Znc) Net Current  Cmos  Bang-bang Phase Detector (Bbpd)  
A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation Journal article
Wang, Lin, Chen, Yong, Yang, Chaowei, Zhou, Xionghui, Han, Mei, Stefano, Crovetti Paolo, Mak, Pui In, Martins, Rui P.. A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation[J]. International Journal of Circuit Theory and Applications, 2023, 51(5), 1988-2015.
Authors:  Wang, Lin;  Chen, Yong;  Yang, Chaowei;  Zhou, Xionghui;  Han, Mei; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:1.8/1.7 | Submit date：2023/06/05
Bang-bang Clock And Data Recovery (Bbcdr)  Current Mismatch  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Phase Interpolator (Pi)  R-2r Digital-to-analog Converter (Dac)  Ring Oscillator (Ro)  Switched-capacitor (Sc) Array  Wide Capture Range  
A 3.57-mW 2.88-GHz Multi-Phase Injection-Locked Ring-VCO with a 200-kHz 1/f3 Phase Noise Corner Journal article
Fan, Chao, Zhao, Ya, Zhang, Yanlong, Yin, Jun, Geng, Li, Mak, Pui In. A 3.57-mW 2.88-GHz Multi-Phase Injection-Locked Ring-VCO with a 200-kHz 1/f3 Phase Noise Corner[J]. IEEE Transactions on Circuits and Systems II - Express Briefs, 2022, 70(3), 865-869.
Authors:  Fan, Chao;  Zhao, Ya;  Zhang, Yanlong;  Yin, Jun;  Geng, Li; et al.
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:4.0/3.7 | Submit date：2023/01/30
Cmos  Ring Voltage-controlled Oscillator (Rvco)  Phase Noise  Flicker Noise  1/f3 Phase Noise Corner  Inherent Low-frequency Output  Multi-phase Injection Locking (Mpil)  Clock Generation  
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference Journal article
Yu Duan, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins. Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(12), 4799-4809.
Authors:  Yu Duan;  Chi-Hang Chan;  Yan Zhu;  Rui Paulo Martins
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:5.2/4.5 | Submit date：2023/01/30
Digital-regulated Supply Noise Cancellation (Dsnc)  Interference Reduction  Jitter  Phase Noise Cancellation (Pnc)  Phase-locked Loop  Phase-locked Loop (Pll)  Ring Voltage-controlled Oscillator (Rvco)  Supply Noise Suppression  
A 0.15-V, 44.73% PCE charge pump with CMOS differential ring-VCO for energy harvesting systems Journal article
Pakkirisami Churchill, Kishore Kumar, Ramiah, Harikrishnan, Chong, Gabriel, Ahmad, Mohd Yazed, Yin, Jun, Mak, Pui In, Martins, Rui P.. A 0.15-V, 44.73% PCE charge pump with CMOS differential ring-VCO for energy harvesting systems[J]. Analog Integrated Circuits and Signal Processing, 2022, 111(1), 35-43.
Authors:  Pakkirisami Churchill, Kishore Kumar;  Ramiah, Harikrishnan;  Chong, Gabriel;  Ahmad, Mohd Yazed;  Yin, Jun; et al.
Favorite | TC[WOS]:6 TC[Scopus]:8  IF:1.2/1.0 | Submit date：2022/05/04
Charge Pump  Dc-to-dc Conversion  Dynamic Voltage Frequency Scaling (Dvfs)  Energy Harvesting  Ring-voltage ContRolled Oscillator (Ro)  
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop Journal article
Liu, Yueduo, Bao, Rongxin, Zhu, Zihao, Yang, Shiheng, Zhou, Xiong, Li, Qiang, Yin, Jun, Mak, Pui In. Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(2), 495-505.
Authors:  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2022/03/04
Voltage-controlled Oscillators  Jitter  Clocks  Phase Noise (Pn)  Topology  Performance Evaluation  Delays  Figure Of Merit (Fom)  Injection-locked Clock Multiplier (Ilcm)  Multiplying Delay-locked Loop (Mdll)  Power  Ring Voltage-controlled Oscillator (Rvco)