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FPGA-based decoupled double synchronous reference frame PLL for active power filters
Conference paper
Bo Sun, Ning-Yi Dai, U-Fat Chio, Man-Chung Wong, Chi-Kong Wong, Sai-Weng Sin, Seng-Pan U, R. P. Martins. FPGA-based decoupled double synchronous reference frame PLL for active power filters[C]. IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2011, 2145-2150.
Authors:
Bo Sun
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Ning-Yi Dai
;
U-Fat Chio
;
Man-Chung Wong
;
Chi-Kong Wong
; et al.
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Submit date：2018/12/23
Decoupled Double Synchronous Reference Frame Phase-locked Loop (Ddsrf-pll)
Field-programmable Gate Array (Fpga)
Shunt Active Power Filter (Sapf)
