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28.3 A 12-28V to 0.6-1.8V Ratio-Regulatable Dickson SC Converter with Dual-Mode Phase Misalignment Operations Achieving 93.1% Efficiency and 6A Output Conference paper
Ma, Qiaobo, Jiang, Yang, Li, Huihua, Zhang, Xiongjie, Law, Man Kay, Martins, Rui P., Mak, Pui In. 28.3 A 12-28V to 0.6-1.8V Ratio-Regulatable Dickson SC Converter with Dual-Mode Phase Misalignment Operations Achieving 93.1% Efficiency and 6A Output[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 460-462.
Authors:  Ma, Qiaobo;  Jiang, Yang;  Li, Huihua;  Zhang, Xiongjie;  Law, Man Kay; et al.
Favorite | TC[Scopus]:1 | Submit date：2024/05/16
Switches  Universal Serial Bus  Regulation  Topology  System-on-chip  Solid State Circuits  Inductors  
17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM Conference paper
Tan, Fei, Yu, Wei Han, Lin, Jinhai, Un, Ka Fai, Martins, Rui P., Mak, Pui In. 17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 330-332.
Authors:  Tan, Fei;  Yu, Wei Han;  Lin, Jinhai;  Un, Ka Fai;  Martins, Rui P.; et al.
Favorite | TC[Scopus]:1 | Submit date：2024/05/16
Computational Modeling  User Experience  Hardware  Computational Efficiency  Solid State Circuits  
34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC Conference paper
Yuan, Yiyang, Yang, Yiming, Wang, Xinghua, Li, Xiaoran, Ma, Cailian, Chen, Qirui, Tang, Meini, Wei, Xi, Hou, Zhixian, Zhu, Jialiang, Wu, Hao, Ren, Qirui, Xing, Guozhong, Mak, Pui In, Zhang, Feng. 34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 576-578.
Authors:  Yuan, Yiyang;  Yang, Yiming;  Wang, Xinghua;  Li, Xiaoran;  Ma, Cailian; et al.
Favorite | TC[Scopus]:2 | Submit date：2024/05/16
Training  Random Access Memory  Throughput  Common Information Model (Computing)  System-on-chip  Solid State Circuits  Complexity Theory  
3.3 A 0.5V 6.14μW Trimming-Free Single-XO Dual-Output Frequency Reference with [5.1nJ, 120μs] XO Startup and [8.1nJ, 200μs] Successive-Approximation-Based RTC Calibration Conference paper
Luo, Rui, Lei, Ka Meng, Martins, Rui P., Mak, Pui In. 3.3 A 0.5V 6.14μW Trimming-Free Single-XO Dual-Output Frequency Reference with [5.1nJ, 120μs] XO Startup and [8.1nJ, 200μs] Successive-Approximation-Based RTC Calibration[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 58-60.
Authors:  Luo, Rui;  Lei, Ka Meng;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[Scopus]:0 | Submit date：2024/05/16
Training  Costs  Real-time Systems  Calibration  Solid State Circuits  Quartz Crystals  Oscillators  
A dual-output SC converter with dynamic power allocation for multicore application processors, Conference paper
Jiang, J., Lu, Y., Liu, X., Ki, W.-H., Mok, P. K. T., U, S.-P., Martins, R. P.. A dual-output SC converter with dynamic power allocation for multicore application processors,[C], 2018.
Authors:  Jiang, J.;  Lu, Y.;  Liu, X.;  Ki, W.-H.;  Mok, P. K. T.; et al.
Favorite |  | Submit date：2022/01/24
Solid state circuits  Dynamic scheduling  Resource management  Very large scale integration