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2024 [1]
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A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM
Journal article
Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Feng, Chaoping, Chen, Tianle, Zhang, Xinming, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Iizuka, Tetsuya, Chen, Yong, Mak, Pui In, Han, Zhengsheng, Li, Bo. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551.
Authors:
Ren, Hongyu
;
Yang, Zunsong
;
Huang, Yunbo
;
Feng, Chaoping
;
Chen, Tianle
; et al.
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Submit date：2024/05/16
Double Sampling (Ds)
Figure Of Merit (Fom)
Frequency Synthesizer
Low Jitter
Low Spur
Phase Detector (Pd)
Phase-locked Loop (Pll)
Phase Noise (Pn)
Reference Sampling (Rs)
Subsampling (Ss)
Phase Locked Loops
Type-i
