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An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC with Dual-Path Time-Assisted Residue Generation Scheme Journal article
Hao, Junyan, Zhang, Minglei, Liu, Zijian, Zhang, Yanbo, Liu, Shubin, Zhu, Zhangming, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC with Dual-Path Time-Assisted Residue Generation Scheme[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Hao, Junyan;  Zhang, Minglei;  Liu, Zijian;  Zhang, Yanbo;  Liu, Shubin; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/12/26
Analog-to-digital Converter (Adc)  Parallel Quantization And Amplification  Pipelined Adc  Time-domain (Td) Adc  Voltage-to-time Converter (Vtc)  
A 0.004-mm2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS Journal article
Zhang,Chenghao, Wei,Jiangbo, Chen,Yong, Liu,Maliang, Yang,Yintang. A 0.004-mm2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2023, 58(11), 3179-3193.
Authors:  Zhang,Chenghao;  Wei,Jiangbo;  Chen,Yong;  Liu,Maliang;  Yang,Yintang
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2023/08/03
Analog-to-digital Converter (Adc)  Calibration  Cmos  Folding  Gated Ring Oscillator (Gro)  Interpolation  Pulse Generator (Pg)  Time Domain (Td)  Voltage Domain (Vd)