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A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration Conference paper
Song, Y., Zhu, Y., Chan, C. H., Martins, R. P.. A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration[C], 2020.
Authors:  Song, Y.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
analogue-digital conversion  calibration  CMOS digital integrated circuits  digital-analogue conversion  low-power electronics  preamplifiers  background inter-stage offset calibration  noise-shaping SAR hybrid architecture  NS-SAR  SNDR  power-hungry preamplifiers  low-noise targets  Schreier FoM  0-1 MASH SDM  pipeline-SAR structure  single-channel ADC  power-hungry residue amplifier  ADC power  area-hungry bit weight calibration  dynamic amplifier  pipeline operation  power efficiency  partial interleaving structu  
FreePipe: a Programmable Parallel Rendering Architecture for Efficient Multi-Fragment Effects Conference paper
Liu, Fang, Huang, Meng-Cheng, Liu, Xue-Hui, Wu, En-Hua. FreePipe: a Programmable Parallel Rendering Architecture for Efficient Multi-Fragment Effects[C]. Association for Computing Machinery, 2010, 75-82.
Authors:  Liu, Fang;  Huang, Meng-Cheng;  Liu, Xue-Hui;  Wu, En-Hua
Favorite | TC[Scopus]:62 | Submit date：2018/11/06
Depth Peeling  Compute Unified Device Architecture (Cuda)  Graphics Hardware  Programmable Graphics Pipeline  Rasterizer  Multi-fragment Effects  Order-independent Transparency  Atomic Operation