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Conference paper [1]
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2020 [1]
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英語English [1]
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2020 IEEE Intern... [1]
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A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration
Conference paper
Song, Y., Zhu, Y., Chan, C. H., Martins, R. P.. A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration[C], 2020.
Authors:
Song, Y.
;
Zhu, Y.
;
Chan, C. H.
;
Martins, R. P.
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Submit date：2022/01/25
analogue-digital conversion
calibration
CMOS digital integrated circuits
digital-analogue conversion
low-power electronics
preamplifiers
background inter-stage offset calibration
noise-shaping SAR hybrid architecture
NS-SAR
SNDR
power-hungry preamplifiers
low-noise targets
Schreier FoM
0-1 MASH SDM
pipeline-SAR structure
single-channel ADC
power-hungry residue amplifier
ADC power
area-hungry bit weight calibration
dynamic amplifier
pipeline operation
power efficiency
partial interleaving structu
