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A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator Journal article
Zhang, Hongshuai, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator[J]. IEEE Journal of Solid-State Circuits, 2023, 58(12), 3565-3575.
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:2 TC[Scopus]:4  IF:4.6/5.6 | Submit date：2024/01/02
Analog-to-digital Converter (Adc)  Auxiliary Noise Shaping (Ns) Successive-approximation Register (Sar) Adc  Capacitor Stacking  Data-weighted Averaging And detect-And-skip (Dwa And Das)  Differential Sampling  Energy Efficient  Error SupprEssion (Es) And Reconstruction  Gain Error Shaping (Ges)  Partial Time Interleaving  Passive Ns  Pipelined Sar  Quantization Predication Unrolled  Two-step Floating Inverter Amplifier (Fia)  
A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time-Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward Journal article
Zhao,Shulin, Guo,Mingqiang, Qi,Liang, Xu,Dengke, Wang,Guoxing, Martins,Rui P., Sin,Sai Weng. A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time-Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward[J]. IEEE Journal of Solid-State Circuits, 2023, 58(10), 2722-2732.
Authors:  Zhao,Shulin;  Guo,Mingqiang;  Qi,Liang;  Xu,Dengke;  Wang,Guoxing; et al.
Adobe PDF | Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2023/08/03
Error-feedforward (Ff)  Midway Error-feedback (Fb)  Noise Transfer Function (Ntf) Peaking  Offset Reduction  Redundancy  Time-interleaving Noise-shaping Successive Approximation Register (Ns-sar)  
Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs Journal article
Jiang, D., Sin, S. W., Qi, L., Wang, G., Martins, R. P.. Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs[J]. IEEE Open Journal of the Solid-State Circuits Society, 2021, 129-139.
Authors:  Jiang, D.;  Sin, S. W.;  Qi, L.;  Wang, G.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
ADC  analog-to-digital converter  DAC  digital-to-analog-converter  hybrid ADC  incremental ADC (I-ADC)  delta-sigma modulator  time-Interleaving  extrapolating  noise shaping  successive approximation register  SAR.  
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC Journal article
Song,Yan, Zhu,Yan, Chan,Chi Hang, Martins,Rui P.. A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC[J]. IEEE Journal of Solid-State Circuits, 2021, 56(6), 1772-1783.
Authors:  Song,Yan;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite | TC[WOS]:14 TC[Scopus]:17  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Noise-shaping (Ns)  Offset Calibration  Successive Approximation Register (Sar)-assisted Pipeline  Time Interleaving  
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
Chan, Chi-Hang, Zhu, Yan, Zhang, Wai-Hong, Seng-Pan, U., Martins, Rui Paulo. A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53(3), 850-860.
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite | TC[WOS]:60 TC[Scopus]:66  IF:4.6/5.6 | Submit date：2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
Split-Based Time-interleaved ADC with Digital Background Timing-skew Calibration Conference paper
Guo Mingqiang, Sin Sai-Weng, U Seng-Pan, Rui P. Martins. Split-Based Time-interleaved ADC with Digital Background Timing-skew Calibration[C]. IEEE:IEEE, 2017.
Authors:  Guo Mingqiang;  Sin Sai-Weng;  U Seng-Pan;  Rui P. Martins
Adobe PDF | Favorite | TC[Scopus]:7 | Submit date：2022/08/20
Adc, Converters, Digital Background Calibration, Time-interleaving, split-Adc, Timing.