16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration

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	16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration
	Chan, C. H.; Zhu, Y.; Ho, I.M.; Zhang, W.H.; Martins, R. P.
	2017-02-01
Source Publication	Solid-State Circuits Conference (ISSCC), 2017 IEEE International
Abstract	Wireless communication systems and Ethernet networks call for moderate-resolution GS/s energy-efficient ADCs. While previous work [1] shows that the multi-bit per cycle SAR ADC can achieve low power due to various hardware reduction techniques, there are still a few limitations that restrain this architecture. First, the pre-charge slows down the logic and the DAC settling, especially during the MSB conversions. Second, unlike the offset among sub-channels of interleaving SAR ADCs, which can be easily calibrated in the background at the ADC backend [2], the offsets of the comparators in multi-bit SAR ADCs lead to a large sub-ranging error. Such offset is often calibrated in the foreground [1][3] but cannot track voltage and temperature (V&T) variations. This paper presents a 1-then-2b/cycle SAR architecture which removes conventional pre-charging and simultaneously minimizes the logic circuitry complexity to that of a 1b/cycle SAR. The comparator offsets are calibrated in the background without any extra phases or input references. With 2× time interleaving, the prototype achieves 2.4GS/s using a 0.9V supply in 28nm CMOS, leading to a 25.3fJ/conv-step Walden FoM at Nyquist input.
Keyword	—Analog-to-digital converter (ADC) successive approximation architecture low power switched-capacitor circuits.
URL	View the original
Language	英語English
The Source to Article	PB_Publication
PUB ID	30487
Document Type	Conference paper
Collection	Faculty of Education INSTITUTE OF MICROELECTRONICS
Corresponding Author	Zhu, Y.
Recommended Citation GB/T 7714	Chan, C. H.,Zhu, Y., Ho, I.M.,et al. 16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration[C], 2017.
APA	Chan, C. H.., Zhu, Y.., Ho, I.M.., Zhang, W.H.., & Martins, R. P. (2017). 16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration. Solid-State Circuits Conference (ISSCC), 2017 IEEE International.

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