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A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity Journal article
Wu, Hao, Chen, Yong, Yuan, Yiyang, Yue, Jinshan, Fu, Xiangqu, Ren, Qirui, Luo, Qing, Mak, Pui In, Wang, Xinghua, Zhang, Feng. A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, 71(2), 689-702.
Authors:  Wu, Hao;  Chen, Yong;  Yuan, Yiyang;  Yue, Jinshan;  Fu, Xiangqu; et al.
Favorite | TC[WOS]:1 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/02/22
Algebraic Sparsity (As)  Cmos  Computing-in-memory (Cim)  Multiply-accumulation (Mac)  Structured Sparsity (Ss)  Super-resolution (Sr)  Texture Sparsity (Ts)  
34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC Conference paper
Yuan, Yiyang, Yang, Yiming, Wang, Xinghua, Li, Xiaoran, Ma, Cailian, Chen, Qirui, Tang, Meini, Wei, Xi, Hou, Zhixian, Zhu, Jialiang, Wu, Hao, Ren, Qirui, Xing, Guozhong, Mak, Pui In, Zhang, Feng. 34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 576-578.
Authors:  Yuan, Yiyang;  Yang, Yiming;  Wang, Xinghua;  Li, Xiaoran;  Ma, Cailian; et al.
Favorite | TC[Scopus]:2 | Submit date：2024/05/16
P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer Journal article
Fu, Xiangqu, Ren, Qirui, Wu, Hao, Xiang, Feibin, Luo, Qing, Yue, Jinshan, Chen, Yong, Zhang, Feng. P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4938-4948.
Authors:  Fu, Xiangqu;  Ren, Qirui;  Wu, Hao;  Xiang, Feibin;  Luo, Qing; et al.
Favorite | TC[WOS]:3 TC[Scopus]:3  IF:5.2/4.5 | Submit date：2024/02/22
Accelerator  Cmos  Computing-in-memory (Cim)  Dynamic Prune  Prediction Network  Vision Transformer (Vit)  
A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF Journal article
Qirui Ren, Qiang Huo, Zhisheng Chen, Qi Gao, Yiming Wang, Yiming Yang, Hao Wu, Xiangqu Fu, Xiaoxin Xu, Qing Luo, Jianfeng Gao, Chengying Chen, Xiaojin Zhao, Dengyun Lei, Xinghua Wang, Feng Zhang, Yong Chen, Pui-In Mak. A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 31(2), 243-252.
Authors:  Qirui Ren;  Qiang Huo;  Zhisheng Chen;  Qi Gao;  Yiming Wang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:2.8/2.8 | Submit date：2023/01/30
Current Sense Amplifier (Csa)  Low Cost  Low Power  Physical Unclonable Function (Puf)  Radio Frequency Identification Technology (Rfid)  Resistive Ram (rRam)  Security  
A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection Journal article
Ren, Qirui, Chen, Chengying, Dong, Danian, Xu, Xiaoxin, Chen, Yong, Zhang, Feng. A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection[J]. Sensors, 2022, 22(16), 6096.
Authors:  Ren, Qirui;  Chen, Chengying;  Dong, Danian;  Xu, Xiaoxin;  Chen, Yong; et al.
Favorite | TC[WOS]:4 TC[Scopus]:4  IF:3.4/3.7 | Submit date：2023/01/30
Analog Front-end (Afe)  Cmos  Eeg  Rram-based Lowpass Fir Filter  Signal Process  Ultra-low Power