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A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity Journal article
Wu, Hao, Chen, Yong, Yuan, Yiyang, Yue, Jinshan, Fu, Xiangqu, Ren, Qirui, Luo, Qing, Mak, Pui In, Wang, Xinghua, Zhang, Feng. A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, 71(2), 689-702.
Authors:  Wu, Hao;  Chen, Yong;  Yuan, Yiyang;  Yue, Jinshan;  Fu, Xiangqu; et al.
Favorite | TC[WOS]:1 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/02/22
Algebraic Sparsity (As)  Cmos  Computing-in-memory (Cim)  Multiply-accumulation (Mac)  Structured Sparsity (Ss)  Super-resolution (Sr)  Texture Sparsity (Ts)  
A 0.0035-mm20.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE Conference paper
Zhang, Zhaoyu, Zhang, Zhao, Chen, Yong, Wang, Guoqing, Shen, Xinyu, Qi, Nan, Li, Guike, Yu, Shuangming, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 0.0035-mm20.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE[C], New York, USA:IEEE, 2023, 177-180.
Authors:  Zhang, Zhaoyu;  Zhang, Zhao;  Chen, Yong;  Wang, Guoqing;  Shen, Xinyu; et al.
Favorite | TC[WOS]:0 TC[Scopus]:1 | Submit date：2024/02/22
Charge Sharing Integrator  Clock And Data Recovery (Cdr)  Cmos  Continuous-rate  Reference-less  
A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O Journal article
Chen, Sikai, You, Mingyang, Yang, Yunqi, Jin, Ye, Lin, Ziyi, Li, Yihong, Li, Leliang, Li, Guike, Xie, Yujun, Zhang, Zhao, Wang, Binhao, Tang, Ningfeng, Liu, Faju, Fang, Zheyu, Liu, Jian, Wu, Nanjian, Chen, Yong, Liu, Liyuan, Zhu, Ninghua, Li, Ming, Qi, Nan. A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(11), 4271-4282.
Authors:  Chen, Sikai;  You, Mingyang;  Yang, Yunqi;  Jin, Ye;  Lin, Ziyi; et al.
Favorite | TC[WOS]:3 TC[Scopus]:3  IF:5.2/4.5 | Submit date：2023/12/04
Baud-rate  Cdr  Chiplet  Cmos  Multi-chip Module (Mcm)  Optical I/o  Optical Receiver  Silicon Photonics  Tia  
A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces Conference paper
MoonHyung Jang, Wei-Han Yu, Changuk Lee, Maddy Hays, Pingyu Wang, Nick Vitale, Pulkit Tandon, Pumiao Yan, Pui-In Mak, Youngcheol Chae, E.J. Chichilnisky, Boris Murmann, Dante G. Muratore. A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces[C], IEEE Xplore:IEEE, 2023.
Authors:  MoonHyung Jang;  Wei-Han Yu;  Changuk Lee;  Maddy Hays;  Pingyu Wang; et al.
Favorite | TC[Scopus]:5 | Submit date：2023/08/02
Brain  Compression  Interface  Neural  Recording  
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique Journal article
Wang,Lin, Chen,Yong, Yang,Chaowei, Zhao,Xiaoteng, Mak,Pui In, Maloberti,Franco, Martins,Rui P.. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(7), 2637-2650.
Authors:  Wang,Lin;  Chen,Yong;  Yang,Chaowei;  Zhao,Xiaoteng;  Mak,Pui In; et al.
Favorite | TC[WOS]:1 TC[Scopus]:4  IF:5.2/4.5 | Submit date：2023/08/03
Bang-bang Clock And Data Recovery (Bbcdr)  Wide Capture Range  Single Loop  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Deliberate Current Mismatch  Ring Oscillator (Ro)  R-2r Dac  Positive (Pnc)  Negative (Nnc) And Zero (Znc) Net Current  Cmos  Bang-bang Phase Detector (Bbpd)  
A 90- to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor Journal article
Wang, Xi, Wei, Dong, Zhang, Zhiyang, Wu, Tianxiang, Chen, Xu, Chen, Yong, Ren, Junyan, Ma, Shunli. A 90- to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor[J]. International Journal of Circuit Theory and Applications, 2023, 51(4), 1530-1547.
Authors:  Wang, Xi;  Wei, Dong;  Zhang, Zhiyang;  Wu, Tianxiang;  Chen, Xu; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:1.8/1.7 | Submit date：2023/01/30
Imaging System  Low-noise Amplifier (Lna)  Peak-staggered Matching Technique  Superheterodyne Receiver (Rx)  Symmetrical-layout Mixer  Transistor-layout Optimization  W-band  Wideband  
A 4.5-W, 18.5–24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique Journal article
Yujia, Wang, Jincheng, Zhang, Yong, Chen, Junyan, Ren, Shunli, Ma. A 4.5-W, 18.5–24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, 31(2), 233-242.
Authors:  Yujia, Wang;  Jincheng, Zhang;  Yong, Chen;  Junyan, Ren;  Shunli, Ma
Favorite | TC[WOS]:2 TC[Scopus]:5  IF:2.8/2.8 | Submit date：2023/01/30
Chebyshev Matching Technique  Gallium Nitride (Gan)  Power Added Efficiency (Pae)  Power Amplifier (Pa)  Satellite Communication  Wideband Matching Network  
A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation Journal article
Wang, Lin, Chen, Yong, Yang, Chaowei, Zhou, Xionghui, Han, Mei, Stefano, Crovetti Paolo, Mak, Pui In, Martins, Rui P.. A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation[J]. International Journal of Circuit Theory and Applications, 2023, 51(5), 1988-2015.
Authors:  Wang, Lin;  Chen, Yong;  Yang, Chaowei;  Zhou, Xionghui;  Han, Mei; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:1.8/1.7 | Submit date：2023/06/05
Bang-bang Clock And Data Recovery (Bbcdr)  Current Mismatch  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Phase Interpolator (Pi)  R-2r Digital-to-analog Converter (Dac)  Ring Oscillator (Ro)  Switched-capacitor (Sc) Array  Wide Capture Range  
A 124-to-152-GHz Power Amplifier Exploiting Chebyshev-Type Two-Section Wideband and Low-Loss Power-Combining Technique in 28-nm CMOS Journal article
Zhang, Jincheng, Wang, Yujia, Chen, Yong, Ren, Junyan, Ma, Shunli. A 124-to-152-GHz Power Amplifier Exploiting Chebyshev-Type Two-Section Wideband and Low-Loss Power-Combining Technique in 28-nm CMOS[J]. IEEE Transactions on Microwave Theory and Techniques, 2022, 71(5), 1852-1865.
Authors:  Zhang, Jincheng;  Wang, Yujia;  Chen, Yong;  Ren, Junyan;  Ma, Shunli
Favorite | TC[WOS]:10 TC[Scopus]:10  IF:4.1/4.2 | Submit date：2023/06/05
Chebyshev  Cmos  Coupled Resonator  D-band  Power Amplifier (Pa)  Slow Wave Coplanar Waveguide (S-cpw)  Transformer  Two-section Wideband Power Combining  
A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF Journal article
Qirui Ren, Qiang Huo, Zhisheng Chen, Qi Gao, Yiming Wang, Yiming Yang, Hao Wu, Xiangqu Fu, Xiaoxin Xu, Qing Luo, Jianfeng Gao, Chengying Chen, Xiaojin Zhao, Dengyun Lei, Xinghua Wang, Feng Zhang, Yong Chen, Pui-In Mak. A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 31(2), 243-252.
Authors:  Qirui Ren;  Qiang Huo;  Zhisheng Chen;  Qi Gao;  Yiming Wang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:2.8/2.8 | Submit date：2023/01/30
Current Sense Amplifier (Csa)  Low Cost  Low Power  Physical Unclonable Function (Puf)  Radio Frequency Identification Technology (Rfid)  Resistive Ram (rRam)  Security