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An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications Journal article
Cao, Rujian, Zhao, Zhongyu, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications[J]. IEEE Transactions on Circuits and Systems II-Express Briefs, 2024, 71(11), 4688-4692.
Authors:  Cao, Rujian;  Zhao, Zhongyu;  Un, Ka Fai;  Yu, Wei Han;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/10/10
Sparse Matrices  Computational Modeling  Transformers  Hardware  Energy Efficiency  Circuits  Throughput  Dataflow  Digital Accelerator  Energy-efficient  Field-programmable Gate Array (Fpga)  Sparsity  Transformer  
N-AquaRAM: A Cost-Efficient Deep Learning Accelerator for Real-Time Aquaponic Monitoring Journal article
Siddique, Ali, Iqbal, Muhammad Azhar, Sun, Jingqi, Zhang, Xu, Vai, Mang I., Siddique, Sunbal. N-AquaRAM: A Cost-Efficient Deep Learning Accelerator for Real-Time Aquaponic Monitoring[J]. Agricultural Research, 2024.
Authors:  Siddique, Ali;  Iqbal, Muhammad Azhar;  Sun, Jingqi;  Zhang, Xu;  Vai, Mang I.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:1.4/1.5 | Submit date：2024/10/10
Aquaculture  Deep Learning Accelerator  Field Programmable Gate Arrays (Fpgas)  Fish Size Estimation  Giga OPerations Per Second (Gops)  Smart Aquaponics  
P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer Journal article
Fu, Xiangqu, Ren, Qirui, Wu, Hao, Xiang, Feibin, Luo, Qing, Yue, Jinshan, Chen, Yong, Zhang, Feng. P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4938-4948.
Authors:  Fu, Xiangqu;  Ren, Qirui;  Wu, Hao;  Xiang, Feibin;  Luo, Qing; et al.
Favorite | TC[WOS]:3 TC[Scopus]:3  IF:5.2/4.5 | Submit date：2024/02/22
Accelerator  Cmos  Computing-in-memory (Cim)  Dynamic Prune  Prediction Network  Vision Transformer (Vit)  
An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications Journal article
Zhao, Zhongyu, Cao, Rujian, Un, Ka Fai, Yu, Wei Han, Mak, Pui In, Martins, Rui P.. An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(1), 281-285.
Authors:  Zhao, Zhongyu;  Cao, Rujian;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In; et al.
Favorite | TC[WOS]:8 TC[Scopus]:12  IF:4.0/3.7 | Submit date：2022/08/08
Transformers  Energy Efficiency  Broadcasting  Convolutional Neural Networks  Integrated Circuit Modeling  Field Programmable Gate Arrays  Random Access Memory  Dataflow  Digital Accelerator  Energy-efficient  Field-programmable Gate Array (Fpga)  Energy Efficiency  Image Recognition  Transformer  
An Energy-Efficient SIFT Based Feature Extraction Accelerator for High Frame-Rate Video Applications Journal article
Liu, Bingqiang, Yin, Zehua, Zhang, Xvpeng, Zhan, Yi, Hu, Xiaofeng, Yu, Guoyi, Zheng, Yuanjin, Wang, Chao, Zou, Xuecheng. An Energy-Efficient SIFT Based Feature Extraction Accelerator for High Frame-Rate Video Applications[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(12), 4930-4943.
Authors:  Liu, Bingqiang;  Yin, Zehua;  Zhang, Xvpeng;  Zhan, Yi;  Hu, Xiaofeng; et al.
Favorite | TC[WOS]:7 TC[Scopus]:9  IF:5.2/4.5 | Submit date：2023/02/27
Feature Extraction  Scale-invariant Feature Transform (Sift)  High Frame Rate  Hardware Accelerator  
Automatic generation of multi-precision multi-arithmetic CNN accelerators for FPGAs Conference paper
Zhao,Yiren, Gao,Xitong, Guo,Xuan, Liu,Junyi, Wang,Erwei, Mullins,Robert, Cheung,Peter Y.K., Constantinides,George, Xu,Cheng Zhong. Automatic generation of multi-precision multi-arithmetic CNN accelerators for FPGAs[C], IEEE COMPUTER SOC, 10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1264 USA:IEEE, 2019, 45-53.
Authors:  Zhao,Yiren;  Gao,Xitong;  Guo,Xuan;  Liu,Junyi;  Wang,Erwei; et al.
Favorite | TC[WOS]:25 TC[Scopus]:31 | Submit date：2021/03/09
Auto-generation  Cnn Hardware Accelerator  
Hardware-accelerated implementation of EMD Conference paper
Wang L., Vai M.I., Mak P.U., Ieong C.I.. Hardware-accelerated implementation of EMD[C], 2010, 912-915.
Authors:  Wang L.;  Vai M.I.;  Mak P.U.;  Ieong C.I.
Favorite | TC[WOS]:13 TC[Scopus]:28 | Submit date：2019/02/14
Emd  Fpga  Hardware Accelerator  Hht  Imf  Nios Ii