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THE STATE KEY LA... [5]
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A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique
Journal article
Wang,Lin, Chen,Yong, Yang,Chaowei, Zhao,Xiaoteng, Mak,Pui In, Maloberti,Franco, Martins,Rui P.. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(7), 2637-2650.
Authors:
Wang,Lin
;
Chen,Yong
;
Yang,Chaowei
;
Zhao,Xiaoteng
;
Mak,Pui In
; et al.
Favorite
|
TC[WOS]:
1
TC[Scopus]:
4
IF:
5.2
/
4.5
|
Submit date:2023/08/03
Bang-bang Clock And Data Recovery (Bbcdr)
Wide Capture Range
Single Loop
Frequency Detector (Fd)
Hybrid Control Circuit (Hcc)
Deliberate Current Mismatch
Ring Oscillator (Ro)
R-2r Dac
Positive (Pnc)
Negative (Nnc) And Zero (Znc) Net Current
Cmos
Bang-bang Phase Detector (Bbpd)
A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector
Conference paper
Ge, Xinyi, Chen, Yong, Wang, Lin, Qi, Nan, Mak, Pui In, Martins, Rui P.. A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector[C]:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2022.
Authors:
Ge, Xinyi
;
Chen, Yong
;
Wang, Lin
;
Qi, Nan
;
Mak, Pui In
; et al.
Favorite
|
TC[WOS]:
4
TC[Scopus]:
5
|
Submit date:2023/01/30
Bang-bang Phase Detector (Bbpd)
Charge Steering
Clock And Data Recovery (Cdr)
Cmos
Half Rate
Non- Return-to-zero (Nrz)
Quadrature Voltage-controlled Oscillator (Qvco)
Return-to-zero (Rz)
Rz-to-nrz Converter
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS
Journal article
Zhao,Xiaoteng, Chen,Yong, Mak,Pui In, Martins,Rui P.. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68(1), 89-102.
Authors:
Zhao,Xiaoteng
;
Chen,Yong
;
Mak,Pui In
;
Martins,Rui P.
Favorite
|
TC[WOS]:
21
TC[Scopus]:
21
IF:
5.2
/
4.5
|
Submit date:2021/03/09
Bang- Bang Clock And Data Recovery (Bbcdr)
Bang-bang Phase Detector (Bbpd)
Cmos
Four- And Eight-level Pulse Amplitude Modulation (Pam-4/-8)
Half Rate
Hogge And alexAnder Pd
Jitter Tolerance (Jtol).
Jitter Transfer Function (Jtf)
Non-return-to-zero (Nrz)
Strongarm Comparator
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS
Conference paper
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui P. Martins. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS[C]:IEEE, 2019, 229-232.
Authors:
Xiaoteng Zhao
;
Yong Chen
;
Pui-In Mak
;
Rui P. Martins
Favorite
|
TC[WOS]:
6
TC[Scopus]:
7
|
Submit date:2021/03/09
4-/8-level Pulse Amplitude Modulation (Pam-4/8)
Bang-bang Phase Detector (Bbpd)
Clock And Data Recovery (Cdr)
Half Rate
Non-return To Zero (Nrz)
Strongarm Comparator
Voltage-to-current (V/i) Converter
Xor
Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter
Journal article
Ge,Xinyi, Chen,Yong, Zhao,Xiaoteng, Mak,Pui In, Martins,Rui P.. Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(10), 2223-2236.
Authors:
Ge,Xinyi
;
Chen,Yong
;
Zhao,Xiaoteng
;
Mak,Pui In
;
Martins,Rui P.
Favorite
|
TC[WOS]:
19
TC[Scopus]:
19
IF:
2.8
/
2.8
|
Submit date:2021/03/09
Bang-bang Clock And Data Recovery (Bbcdr)
Bang-bang Phase Detector (Bbpd)
Binary
Fourier Series
Jitter Generation (Jgen)
Jitter Tolerance (Jtol)
Jitter Transfer Function (Jtf)
Linear Phase Detector
Loop Filter (Lf)
Sinking Area