English | 繁體

Search in the results

UM

Browse/Search Results:  1-5 of 5 Help

Selected(0)Clear Items/Page:    Sort:
Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL Journal article
Song, Jingrun, Yang, Xinyu, Liu, Jiaxu, Liu, Yueduo, Zhu, Zihao, Han, Zhengxuan, Zhang, Zehao, Liu, Jiaxin, Zhang, Hongshuai, Yin, Jun, Mak, Pui In, Yang, Shiheng. Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
Authors:  Song, Jingrun;  Yang, Xinyu;  Liu, Jiaxu;  Liu, Yueduo;  Zhu, Zihao; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/12/26
Charge-sharing Integrator  Hybrid Pll (hPll)  Digital Pll (dPll)  Digitally Controlled Oscillator (Dco)  Jitter  Multi-rate  Nonlinearity  Phase Noise (Pn)  Prediction  Spur  Spectrum  
A 0.0035-mm20.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE Conference paper
Zhang, Zhaoyu, Zhang, Zhao, Chen, Yong, Wang, Guoqing, Shen, Xinyu, Qi, Nan, Li, Guike, Yu, Shuangming, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 0.0035-mm20.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE[C], New York, USA:IEEE, 2023, 177-180.
Authors:  Zhang, Zhaoyu;  Zhang, Zhao;  Chen, Yong;  Wang, Guoqing;  Shen, Xinyu; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1 | Submit date：2024/02/22
Charge Sharing Integrator  Clock And Data Recovery (Cdr)  Cmos  Continuous-rate  Reference-less  
A 600-µm2 Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
Yang, Shiheng, Yin, Jun, Xu, Tailong, Yi, Taimo, Mak, Pui-In, Li, Qiang, Martins, Rui P.. A 600-µm2 Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68(9), 3108 - 3112.
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui-In; et al.
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:4.0/3.7 | Submit date：2022/01/25
Area  Analog Phase-locked Loop (Pll)  Cmos  Charge-sharing Integrator  Digital Pll  Hybrid Pll  Integrator  Integer-n  Jitter  Ring Oscillator  Ultra-low Power  
A 600-µm2 Ring-VCO-Based Type-II Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
Yang, Shiheng, Yin, Jun, Xu, Tailong, Yi, Taimo, Mak, Pui-In, Li, Qiang, Martins, Rui P.. A 600-µm2 Ring-VCO-Based Type-II Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68(9), 3108-3112.
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui-In; et al.
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:4.0/3.7 | Submit date：2022/08/19
Area  Analog Phase-locked Loop (Pll)  Cmos  Charge-sharing Integrator  Digital Pll  Hybrid Pll  Integrator  Integer-n  Jitter  Ring Oscillator  Ultra-low Power  
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
Yang, Shiheng, Yin, Jun, Xu, Tailong, Yi, Taimo, Mak, Pui In, Li, Qiang, Martins, Rui P.. A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68(9), 3108-3112.
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In; et al.
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:4.0/3.7 | Submit date：2021/09/20
Analog Phase-locked Loop (Pll)  Area  Charge-sharing Integrator  Cmos  Digital Pll  Hybrid Pll  Integer-n  Integrator  Jitter  Ring Oscillator  Ultra-low Power