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A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique Journal article
Wang,Lin, Chen,Yong, Yang,Chaowei, Zhao,Xiaoteng, Mak,Pui In, Maloberti,Franco, Martins,Rui P.. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(7), 2637-2650.
Authors:  Wang,Lin;  Chen,Yong;  Yang,Chaowei;  Zhao,Xiaoteng;  Mak,Pui In; et al.
Favorite | TC[WOS]:1 TC[Scopus]:4  IF:5.2/4.5 | Submit date：2023/08/03
Bang-bang Clock And Data Recovery (Bbcdr)  Wide Capture Range  Single Loop  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Deliberate Current Mismatch  Ring Oscillator (Ro)  R-2r Dac  Positive (Pnc)  Negative (Nnc) And Zero (Znc) Net Current  Cmos  Bang-bang Phase Detector (Bbpd)  
A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation Journal article
Wang, Lin, Chen, Yong, Yang, Chaowei, Zhou, Xionghui, Han, Mei, Stefano, Crovetti Paolo, Mak, Pui In, Martins, Rui P.. A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation[J]. International Journal of Circuit Theory and Applications, 2023, 51(5), 1988-2015.
Authors:  Wang, Lin;  Chen, Yong;  Yang, Chaowei;  Zhou, Xionghui;  Han, Mei; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:1.8/1.7 | Submit date：2023/06/05
Bang-bang Clock And Data Recovery (Bbcdr)  Current Mismatch  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Phase Interpolator (Pi)  R-2r Digital-to-analog Converter (Dac)  Ring Oscillator (Ro)  Switched-capacitor (Sc) Array  Wide Capture Range  
A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme Conference paper
Wang, Lin, Chen, Yong, Yang, Chaowei, Zhao, Xiaoteng, Mak, Pui In, Maloberti, Franco, Martins, Rui P.. A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme[C]:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2022.
Authors:  Wang, Lin;  Chen, Yong;  Yang, Chaowei;  Zhao, Xiaoteng;  Mak, Pui In; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1 | Submit date：2023/03/06
Hybrid Control Circuit (Hcc)  Deliberate Current Mismatch  Charge Pump (Cp)  Ring Oscillator (Ro)  R-2r Dac  Positive (Pnc)  Negative (Nnc)  Zero (Znc) Net Current  
A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array Journal article
Dong, Li, Song, Yan, Xie, Yi, Xin, Youze, Li, Ken, Jing, Xixin, Zhang, Bing, Gui, Xiaoyan, Geng, Li. A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array[J]. Microelectronics Journal, 2021, 113, 105109.
Authors:  Dong, Li;  Song, Yan;  Xie, Yi;  Xin, Youze;  Li, Ken; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:1.9/1.7 | Submit date：2021/12/08
Analog-to-digital Converter (Adc)  Area-efficient  Dac Mismatch  High Linearity  Insensitive Geometry  
Digital Assisted Techniques for Bridge DAC Capacitor Mismatch Calibration in SAR ADC Thesis
Wang , G.C., Zhu, Y., Chan, C. H., U, S.P.. Digital Assisted Techniques for Bridge DAC Capacitor Mismatch Calibration in SAR ADC[D], 2017.
Authors:  Wang , G.C.;  Zhu, Y.;  Chan, C. H.;  U, S.P.
Favorite |  | Submit date：2023/08/31
Bridge DAC  Capacitor Mismatch Calibration  SAR ADC  
A high resolution multi-bit incremental converter insensitive to DAC mismatch error Conference paper
Biao Wang, Sai-Weng Sin, Seng-Pan U, R. P. Martins. A high resolution multi-bit incremental converter insensitive to DAC mismatch error[C], 2016.
Authors:  Biao Wang;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite | TC[WOS]:2 TC[Scopus]:8 | Submit date：2019/02/11
High Resolution  Incremental Converter  Multi-bit Quantizer  Insensitive To Dac Mismatch