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Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction Journal article
Xu, Tailong, Li, Haoran, Meng, Xi, Zhan, Xiangxun, Peng, Yatao, Yin, Jun, Yang, Shiheng, Fan, Chao, Huang, Zhixiang, Martins, Rui P., Mak, Pui In. Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2025.
Authors:  Xu, Tailong;  Li, Haoran;  Meng, Xi;  Zhan, Xiangxun;  Peng, Yatao; et al.
Favorite | TC[Scopus]:0  IF:4.0/3.7 | Submit date：2025/01/22
Gain-boosting phase detector  jitter  phase noise  phase-locked loop  reference spur  reference-sampling  
A 6-to-7.5-GHz 54-fsrmsJitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction Journal article
Xu, Tailong, Zhong, Shenke, Yin, Jun, Mak, Pui In, Martins, Rui P.. A 6-to-7.5-GHz 54-fsrmsJitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(12), 4774-4786.
Authors:  Xu, Tailong;  Zhong, Shenke;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:8 TC[Scopus]:11  IF:5.2/4.5 | Submit date：2023/01/30
Gain-boosting  Low Jitter  Low Phase Noise  Phase-locked Loop (Pll)  Reference Spur  Reference-sampling Phase Detector (Rspd)  Sampling Phase Detector (Spd)  Sub-sampling Phase Detector (Sspd)  Switched-capacitor Voltage Multiplier