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A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array Journal article
Dong, Li, Song, Yan, Xie, Yi, Xin, Youze, Li, Ken, Jing, Xixin, Zhang, Bing, Gui, Xiaoyan, Geng, Li. A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array[J]. Microelectronics Journal, 2021, 113, 105109.
Authors:  Dong, Li;  Song, Yan;  Xie, Yi;  Xin, Youze;  Li, Ken; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:1.9/1.7 | Submit date：2021/12/08
Analog-to-digital Converter (Adc)  Area-efficient  Dac Mismatch  High Linearity  Insensitive Geometry  
A high resolution multi-bit incremental converter insensitive to DAC mismatch error Conference paper
Biao Wang, Sai-Weng Sin, Seng-Pan U, R. P. Martins. A high resolution multi-bit incremental converter insensitive to DAC mismatch error[C], 2016.
Authors:  Biao Wang;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite | TC[WOS]:2 TC[Scopus]:8 | Submit date：2019/02/11
High Resolution  Incremental Converter  Multi-bit Quantizer  Insensitive To Dac Mismatch