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A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur
Journal article
Yunbo Huang, Yong Chen, Bo Zhao, Pui-In Mak, Rui P. Martins. A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 31(2), 188-198.
Authors:
Yunbo Huang
;
Yong Chen
;
Bo Zhao
;
Pui-In Mak
;
Rui P. Martins
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Submit date：2023/02/22
Cmos
Figure-of-merit (Fom)
Harmonic-rich Voltage-controlled Oscillator (Vco)
Integrated Jitter, Phase-detection Gain (Kpd)
Reference (Ref) Feedthrough Suppression
Sampling Phase-locked Loop (S-pll)
Reference (Ref) Feedthrough Suppression
Type-i
Type-ii
