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A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM Conference paper
Shen, Xinyu, Zhang, Zhao, Li, Guike, Chen, Yong, Qi, Nan, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM[C]:IEEE, 2023, 257-260.
Authors:  Shen, Xinyu;  Zhang, Zhao;  Li, Guike;  Chen, Yong;  Qi, Nan; et al.
Favorite | TC[WOS]:0 TC[Scopus]:1 | Submit date：2024/02/22
Cmos.  Fractional-n(Fn)  Loop Bandwidth Tracking  Ring Sampling Phase-locked Loop (Rspll)  Wideband