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ZHU YAN [1]
CHAN CHI HANG [1]
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Journal article [1]
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2018 [1]
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英語English [1]
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Analysis of common-mode interference and jitter of clock receiver circuits with improved topology
Journal article
Yang X., Zhu Y., Chan C.-H., Seng-Pan U., Martins R.P.. Analysis of common-mode interference and jitter of clock receiver circuits with improved topology[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(6), 1819-1829.
Authors:
Yang X.
;
Zhu Y.
;
Chan C.-H.
;
Seng-Pan U.
;
Martins R.P.
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Submit date：2019/02/11
Isf
Low Clock Jitter Circuit
Self-bias
