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A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering Journal article
Li, Ke, Gong, Haoyu, Xianyu, Congzhou, Li, Zhensheng, Qi, Liang, Guo, Mingqiang, Martins, Rui P., Sin, Sai Weng. A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Li, Ke;  Gong, Haoyu;  Xianyu, Congzhou;  Li, Zhensheng;  Qi, Liang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2025/01/13
Analog-to-digital Converter (Adc)  Cascade Of Integrators With Feedforward (Ciff)  Continuous Time (Ct)  Ct Pipeline (Ctp)  Excess Loop Delay (Eld)  Low-pass Filter (Lpf)  Multistage Noise-shaping (Mash)  Offset Calibration  Signal Transfer Function (Stf) Peaking  
A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA Journal article
Tan, Gaofeng, Qin, Xinyu, Liu, Yan, Guo, Mingqiang, Sin, Sai Weng, Wang, Guoxing, Lian, Yong, Qi, Liang. A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4781-4792.
Authors:  Tan, Gaofeng;  Qin, Xinyu;  Liu, Yan;  Guo, Mingqiang;  Sin, Sai Weng; et al.
Favorite | TC[WOS]:3 TC[Scopus]:5  IF:5.2/4.5 | Submit date：2024/02/23
0-x Mash  Analog-to-digital Converter (Adc)  Anti-aliasing Filtering  Continuous Time (Ct)  Maximum Stable Amplitude (Msa)  Multi-stage Noise Shaping (Mash)  
Wideband Continuous-time MASH Delta-Sigma Modulators: A Tutorial Review Journal article
Qi, Liang, Liu, Yuekai, Sin, Sai Weng, Xing, Xinpeng, Wang, Guoxing, Ortmanns, Maurits, Martins, Rui P.. Wideband Continuous-time MASH Delta-Sigma Modulators: A Tutorial Review[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(6), 2623-2628.
Authors:  Qi, Liang;  Liu, Yuekai;  Sin, Sai Weng;  Xing, Xinpeng;  Wang, Guoxing; et al.
Favorite | TC[WOS]:14 TC[Scopus]:14  IF:4.0/3.7 | Submit date：2022/05/17
Delta-sigma Modulator (Dsm)  Continuoustime (Ct)  Multi-stage Noise-shaping (Mash)  Sturdy Mash  Quantization Noise (Qn)  Qn Leakage  Qn Extraction  
Modelling and Analysis of ?S-Modulation-Based Output Spectrum Spur Reduction in Dual-Path Hybrid DC-DC Converters Conference paper
Zhang, Xiongjie, Jiang, Yang, Law, Man Kay, Mak, Pui In, Martins, Rui P.. Modelling and Analysis of ?S-Modulation-Based Output Spectrum Spur Reduction in Dual-Path Hybrid DC-DC Converters[C], 2022, 269-272.
Authors:  Zhang, Xiongjie;  Jiang, Yang;  Law, Man Kay;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2023/03/21
Dc-dc Converter  Dual-path Hybrid  Mash  Output Spectrum  Sigma-delta Modulator  Spur Reduction  
A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC Conference paper
Li, Ke, Sin, Sai Weng, Qi, Liang, Zhao, Weibing, Wang, Guoxing, Martins, R. P.. A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC[C], 2022, 551-555.
Authors:  Li, Ke;  Sin, Sai Weng;  Qi, Liang;  Zhao, Weibing;  Wang, Guoxing; et al.
Favorite | TC[WOS]:3 TC[Scopus]:3 | Submit date：2023/01/30
Delta-sigma Modulator (Dsm)  Hybrid Adc  Multi-stage Noise-shaping (Mash)  Noise-shaping Successive Approximation Register (Ns-sar)  
Discrete-time mash delta-sigma modulator with second-order digital noise coupling for wideband high-resolution applications Conference paper
Qin, Xinyu, Zhang, Jingying, Qi, Liang, Sin, Sai Weng, Martins, Rui P., Wang, Guoxing. Discrete-time mash delta-sigma modulator with second-order digital noise coupling for wideband high-resolution applications[C], 2021.
Authors:  Qin, Xinyu;  Zhang, Jingying;  Qi, Liang;  Sin, Sai Weng;  Martins, Rui P.; et al.
Favorite | TC[WOS]:2 TC[Scopus]:9 | Submit date：2021/09/20
Digital Noise Coupling  Multistage Noise Shaping (Mash)  Noise Leakage  Wideband High-resolution Applications  Δς Modulator (Dsm)  
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration Conference paper
Song, Y., Zhu, Y., Chan, C. H., Martins, R. P.. A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration[C], 2020.
Authors:  Song, Y.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
analogue-digital conversion  calibration  CMOS digital integrated circuits  digital-analogue conversion  low-power electronics  preamplifiers  background inter-stage offset calibration  noise-shaping SAR hybrid architecture  NS-SAR  SNDR  power-hungry preamplifiers  low-noise targets  Schreier FoM  0-1 MASH SDM  pipeline-SAR structure  single-channel ADC  power-hungry residue amplifier  ADC power  area-hungry bit weight calibration  dynamic amplifier  pipeline operation  power efficiency  partial interleaving structu  
A 4.2mW 77.1dB-SNDR 5MHz-BW DT 2-1 MASH ΔΣ Modulator with Multirate Opamp Sharing Journal article
Qi, L., Sin, W., U, S.P., Maloberti, F., Martins, R. P.. A 4.2mW 77.1dB-SNDR 5MHz-BW DT 2-1 MASH ΔΣ Modulator with Multirate Opamp Sharing[J]. IEEE Transactions on Circuits and Systems I - Regular Papers, 2017, 2641-2654.
Authors:  Qi, L.;  Sin, W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/24
Analog-to-digital Converter (Adc)  Discrete-time (Dt) Delta Sigma (Δς) Modulator  Multi-stage Noise Shaping (Mash)  Wideband  Power-efficient  Opamp Sharing  Multirate  Sar Quantizer  
A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Delta Sigma Modulator With Multirate Opamp Sharing Journal article
Liang Qi, Sai-Weng Sin, Seng-Pan, U., Franco Maloberti, Rui Paulo Martins. A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Delta Sigma Modulator With Multirate Opamp Sharing[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64(10), 2641-2654.
Authors:  Liang Qi;  Sai-Weng Sin;  Seng-Pan, U.;  Franco Maloberti;  Rui Paulo Martins
Favorite | TC[WOS]:37 TC[Scopus]:44  IF:5.2/4.5 | Submit date：2018/10/30
Analog-to-digital Converter (Adc)  Discrete-time (Dt) Delta Sigma (Delta Sigma) Modulator  Multi-stage Noise Shaping (Mash)  Wideband  Power-efficient  Opamp Sharing  Multirate  Successive Approximation Register (Sar) Quantizer  
An Expandable and Extendable High-order Semi-MASH Sigma-Delta Modulator Conference paper
Chon-In Lao, Seng-Pan U, R. P. Martins. An Expandable and Extendable High-order Semi-MASH Sigma-Delta Modulator[C], 2006.
Authors:  Chon-In Lao;  Seng-Pan U;  R. P. Martins
Favorite |  | Submit date：2019/02/28
Sigma Delta Simulation  Mash  Analog-to-digital Converter