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2023 [1]
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A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS
Journal article
Yang,Jian, Pan,Quan, Yin,Jun, Mak,Pui In. A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS[J]. IEEE Transactions on Microwave Theory and Techniques, 2023, 71(8), 3596 - 3604.
Authors:
Yang,Jian
;
Pan,Quan
;
Yin,Jun
;
Mak,Pui In
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Submit date：2023/08/03
Charge Pump (Cp)
Clock Generator
Delay-locked Loop (Dll)
Locking Range
Multiphase Clock
Phase Accuracy
