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Proportional-Derivative Control of Discrete-Time Positive Systems: A State-Space Approach Journal article
Liu, Jason J. R., Yang, Nachuan, Kwok, Ka-Wai, Lam, James. Proportional-Derivative Control of Discrete-Time Positive Systems: A State-Space Approach[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2024, 71(10), 4491-4495.
Authors:  Liu, Jason J. R.;  Yang, Nachuan;  Kwok, Ka-Wai;  Lam, James
Favorite | TC[WOS]:0 TC[Scopus]:1  IF:4.0/3.7 | Submit date：2023/06/19
Discrete-time Systems  Pd Control  Positive System  
A Power-Decoupled Three-Phase Current Source Inverter with Model Predictive Control in An Unbalanced Grid Journal article
Liu, Yonghui, Wang, Minghao, Xu, Zhao, Lyu, Xue, Peng, Yang, Wang, Yue. A Power-Decoupled Three-Phase Current Source Inverter with Model Predictive Control in An Unbalanced Grid[J]. International Journal of Electrical Power and Energy Systems, 2024, 157, 109781.
Authors:  Liu, Yonghui;  Wang, Minghao;  Xu, Zhao;  Lyu, Xue;  Peng, Yang; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:5.0/4.6 | Submit date：2024/05/16
Current Source Inverter (Csi)  Model Predictive Control (Mpc)  Power Decoupling (Pd)  Space Vector Pulse Width Modulation (Svpwm)  
Non-fragile PD Control of Linear Time-Delay Positive Discrete-Time Systems Journal article
Liu, Jason J. R., Lam, James, Wang, Xiaomei, Kwok, Ka-Wai. Non-fragile PD Control of Linear Time-Delay Positive Discrete-Time Systems[J]. APPLIED MATHEMATICS AND COMPUTATION, 2023, 452, 128016.
Authors:  Liu, Jason J. R.;  Lam, James;  Wang, Xiaomei;  Kwok, Ka-Wai
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:3.5/3.1 | Submit date：2023/06/19
Discrete-time Linear System  Non-fragile Control  Positive Time-delay System  Pd Control  
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS Journal article
Zhao, Xiaoteng, Chen, Yong, Mak, Pui In, Martins, Rui P.. A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 57(2), 546-561.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:13  IF:4.6/5.6 | Submit date：2021/10/28
Acquisition Speed  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Clocks  Cmos  Detectors  Four-level Pulse Amplitude Modulation (Pam-4)  Frequency Detector (Fd)  Frequency Modulation  Hybrid Control Circuit (Hcc)  Jitter  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Logic Gates  Phase Detector (Pd)  Strobe Point (Sp).  Switches  Voltage-controlled Oscillators