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2024 [1]
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A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS
Journal article
Lu, Xin, Wu, Jiangchao, Wang, Zhao, Xiang, Yifei, Liu, Liyuan, Mak, Pui In, Martins, Rui P., Law, Man Kay. A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(8), 3635 - 3639.
Authors:
Lu, Xin
;
Wu, Jiangchao
;
Wang, Zhao
;
Xiang, Yifei
;
Liu, Liyuan
; et al.
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TC[WOS]:
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Submit date：2024/05/16
Coarse-fine Conversion
Cyclic Time-to-digital Converter (Tdc)
Delays
Gated-ring Oscillator (Gro)
Generators
Image Edge Detection
Logic Gates
Phase Domain Reset
Ring Oscillators
Signal Resolution
Switches
