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Low-Power Nyquist ADCs Book chapter
出自: Analog Circuits and Signal Processing, Switzerland:Springer, 2023, 页码:131-180
Authors:  Minglei Zhang;  Chi-Hang Chan;  Yan Zhu;  Rui P. Martins
Favorite | TC[Scopus]:1 | Submit date：2023/08/03
Analog-to-digital Converter (Adc)  Calibration  Low Supply Voltage  Pipeline  Successive Approximation Register (Sar)  Time-domain Converter (Tdc)  
High-Performance Oversampling ADCs Book chapter
出自: Analog Circuits and Signal Processing, Switzerland:Springer, 2023, 页码:181-218
Authors:  Chi-Hang Chan;  Yan Zhu;  Liang Qi;  Sai Weng Sin;  Maurits Ortmanns; et al.
Favorite | TC[Scopus]:0 | Submit date：2023/08/03
Analog-to-digital Converter (Adc)  Cmos  Continuous-time Dsm (Ct Dsm)  Delta-sigma Modulator (Dsm)  Noise Shaping (Ns)  Oversampling  Pipeline Sar Adc  Successive Approximation Register (Sar)  
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations Journal article
Zhang, Yanbo, Zhang, Jin, Liu, Shubin, Ding, Ruixue, Zhu, Yan, Chan, Chi Hang, Martins, Rui P.. A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations[J]. IEEE Journal of Solid-State Circuits, 2022, 57(3), 745-756.
Authors:  Zhang, Yanbo;  Zhang, Jin;  Liu, Shubin;  Ding, Ruixue;  Zhu, Yan; et al.
Favorite | TC[WOS]:8 TC[Scopus]:11  IF:4.6/5.6 | Submit date：2022/03/28
Analog-to-digital Converter (Adc)  Inter-stage Gain And Offset Calibrations  Noise-shaping (Ns)  Split Adc  Successive Approximation Register (Sar)-assisted Pipeline  
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC Journal article
Song,Yan, Zhu,Yan, Chan,Chi Hang, Martins,Rui P.. A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC[J]. IEEE Journal of Solid-State Circuits, 2021, 56(6), 1772-1783.
Authors:  Song,Yan;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite | TC[WOS]:15 TC[Scopus]:19  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Noise-shaping (Ns)  Offset Calibration  Successive Approximation Register (Sar)-assisted Pipeline  Time Interleaving  
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration Conference paper
Song, Y., Zhu, Y., Chan, C. H., Martins, R. P.. A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration[C], 2020.
Authors:  Song, Y.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
analogue-digital conversion  calibration  CMOS digital integrated circuits  digital-analogue conversion  low-power electronics  preamplifiers  background inter-stage offset calibration  noise-shaping SAR hybrid architecture  NS-SAR  SNDR  power-hungry preamplifiers  low-noise targets  Schreier FoM  0-1 MASH SDM  pipeline-SAR structure  single-channel ADC  power-hungry residue amplifier  ADC power  area-hungry bit weight calibration  dynamic amplifier  pipeline operation  power efficiency  partial interleaving structu  
A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC Journal article
Song,Yan, Chan,Chi Hang, Zhu,Yan, Martins,Rui P.. A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC[J]. IEEE Journal of Solid-State Circuits, 2019, 55(2), 312-321.
Authors:  Song,Yan;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite | TC[WOS]:17 TC[Scopus]:20  IF:4.6/5.6 | Submit date：2021/03/09
Alternative Loading Capacitor (Alc)  Analog-to-digital Converter (Adc)  Multiplying Digital-to-analog Converter (Mdac) Reusing  Noise Shaping (Ns)  Successive Approximation Register (Sar)-assisted Pipeline