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A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer Journal article
Cao, Yuefeng, Zhang, Minglei, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024.
Authors:  Cao, Yuefeng;  Zhang, Minglei;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2024/07/04
Analog-to-digital Converter (Adc)  Process, Supply Voltage, And Temperature (Pvt)-robust  Sturdy Ring Amplifier (sRingamp)  Time-domain Quantizer  Time-to-digital Converter (Tdc)  Voltage-to-time Converter (Vtc)  
A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT Journal article
Xiaofeng Yang, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins. A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(11), 3753-3763.
Authors:  Xiaofeng Yang;  Chi-Hang Chan;  Yan Zhu;  Rui Paulo Martins
Favorite | TC[WOS]:8 TC[Scopus]:8  IF:5.2/4.5 | Submit date：2021/03/04
Calibration-free  Discrete-time  Gain Tracking  Jitter  Open-loop  Phase Noise Cancellation (Pnc)  Phase-locked Loop (Pll)  Pvt  Reference Spur  Ring Voltage-controlled Oscillator (Rvco)  
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC with <1.5-ps Uncalibrated Quantization Steps Journal article
Zhang,Minglei, Zhu,Yan, Chan,Chi Hang, Martins,Rui P.. An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC with <1.5-ps Uncalibrated Quantization Steps[J]. IEEE Journal of Solid-State Circuits, 2020, 55(12), 3225-3235.
Authors:  Zhang,Minglei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite | TC[WOS]:34 TC[Scopus]:38  IF:4.6/5.6 | Submit date：2021/03/04
Analog-to-digital Converter (Adc)  High-speed Adc  Metastability  Process  Supply Voltage  And Temperature (Pvt) Robustness  Time Interpolation  Time Residue  Time-domain Adc  Time-to-digital Converter (Tdc)  
A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques Journal article
Zhang,Minglei, Chan,Chi Hang, Zhu,Yan, Martins,Rui P.. A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques[J]. IEEE Journal of Solid-State Circuits, 2019, 54(12), 3396-3409.
Authors:  Zhang,Minglei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite | TC[WOS]:27 TC[Scopus]:40  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Low Power Supply  Process  Voltage  And Temperature (Pvt) Robustness  Successive Approximation Register (Sar)  Threshold Crossing Detector  Time Residue Generator (Trg)  Time-domain Adc  Time-to-digital Converter (Tdc)  Two-step Tdc  Voltage-to-time Converter (Vtc)  
An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS Journal article
Zhang, Jin, Ren, Xiaoqian, Liu, Shubin, Chan, Chi Hang, Zhu, Zhangming. An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 67(7), 1174-1178.
Authors:  Zhang, Jin;  Ren, Xiaoqian;  Liu, Shubin;  Chan, Chi Hang;  Zhu, Zhangming
Favorite | TC[WOS]:9 TC[Scopus]:18  IF:4.0/3.7 | Submit date：2021/12/06
Analog-to-digital Converter (Adc)  Full Dynamic Adc  Pipelined Successive-approximation-register (Sar)  Pvt-stabilized Dynamic Amplification  Reused Comparator  
A Slew Rate Variation Compensated 2 x VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method Journal article
Lee, Tzung-Je, Tsai, Tsung-Yi, Lin, Wei, Chio, U-Fat, Wang, Chua-Chin. A Slew Rate Variation Compensated 2 x VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2019, 66(1), 116-120.
Authors:  Lee, Tzung-Je;  Tsai, Tsung-Yi;  Lin, Wei;  Chio, U-Fat;  Wang, Chua-Chin
Favorite | TC[WOS]:13 TC[Scopus]:14  IF:4.0/3.7 | Submit date：2019/01/17
I/o Buffer  Mixed-voltage Tolerant  Pvt Variation  Leakage  Slew Rate Compensation  
A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer Journal article
Lee, Tzung-Je, Tsai, Tsung-Yi, Lin, Wei, Chio, U-Fat, Wang, Chua-Chin. A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25(11), 3166-3174.
Authors:  Lee, Tzung-Je;  Tsai, Tsung-Yi;  Lin, Wei;  Chio, U-Fat;  Wang, Chua-Chin
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:2.8/2.8 | Submit date：2018/10/30
Dynamic Leakage Reduction  I/o Buffer  Mixed-voltage Tolerant  Process-voltage-temperature (Pvt) Variation  Slew Rate Compensation  
A Calibration Scheme for Stability of Self-biased Ring Amplifier Conference paper
Yan, Rongshen, Chan, Chi-Hang, Sin, Sai-Weng, Seng-Pan, U., Martins, R. P., Wang, ZH, Xie, WH. A Calibration Scheme for Stability of Self-biased Ring Amplifier[C], 703 KILMAR CRES, OTTAWA, ONTARIO K2T 0B1, CANADA:CLAUSIUS SCIENTIFIC PR INC, 2017, 226-235.
Authors:  Yan, Rongshen;  Chan, Chi-Hang;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, R. P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2018/10/30
Calibration  Self-biased Ring Amplifier  PVT Variations  Oscillation Detection  Programmable Resistor  
Adaptive On/Off Delay-Compensated Active Rectifiers for Wireless Power Transfer Systems Journal article
Cheng L., Ki W.-H., Lu Y., Yim T.-S.. Adaptive On/Off Delay-Compensated Active Rectifiers for Wireless Power Transfer Systems[J]. IEEE Journal of Solid-State Circuits, 2016, 51(3), 712-723.
Authors:  Cheng L.;  Ki W.-H.;  Lu Y.;  Yim T.-S.
Favorite | TC[WOS]:122 TC[Scopus]:135 | Submit date：2019/02/14
Active Rectifier  Comparator Delay  Delay Compensation  Inductive Coupling  Pvt Variations  Resonant Wireless Power Transfer (R-wpt)  Reverse Current Control  
Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced Pull-up/down Network and Inverse-Narrow-Width Techniques Journal article
Li, M., Ieong, C. I., Law, M. K., Mak, P. I., Vai, M. I., Pun, S. H., Martins, R. P.. Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced Pull-up/down Network and Inverse-Narrow-Width Techniques[J]. IEEE Transactions on Very large scale integration systems, 2015, 3119-3123.
Authors:  Li, M.;  Ieong, C. I.;  Law, M. K.;  Mak, P. I.;  Vai, M. I.; et al.
Favorite |   IF:2.8/2.8 | Submit date：2022/01/24
CMOS  Electrocardiography (ECG)  device sizing  finite impulse response (FIR) filter  inverse-narrow-width (INW)  logical effort  process-voltage-temperature (PVT) variations  sub-threshold standard logic library  ultra-low-energy  ultra-low-voltage