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A Subthreshold Operation Series-Parallel Charge Pump Incorporating Dynamic Source-Fed Oscillator for Wide-Input-Voltage Energy Harvesting Application Journal article
Kee, Yong Jack, Ramiah, Harikrishnan, Churchill, Kishore Kumar Pakkirisami, Chong, Gabriel, Mekhilef, Saad, Lai, Nai Shyan, Chen, Yong, Mak, Pui In, Martins, Rui P.. A Subthreshold Operation Series-Parallel Charge Pump Incorporating Dynamic Source-Fed Oscillator for Wide-Input-Voltage Energy Harvesting Application[J]. IEEE Access, 2023, 11, 97641-97653.
Authors:  Kee, Yong Jack;  Ramiah, Harikrishnan;  Churchill, Kishore Kumar Pakkirisami;  Chong, Gabriel;  Mekhilef, Saad; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:3.4/3.7 | Submit date：2024/02/22
Cmos  Dc-to-dc Converter  Low Power Energy Harvesting  Power Conversion Efficiency (Pce)  Reconfigurable Charge Pump (Cp)  Ring-voltage Controlled Oscillator (Rvco)  
A 3.57-mW 2.88-GHz Multi-Phase Injection-Locked Ring-VCO with a 200-kHz 1/f3 Phase Noise Corner Journal article
Fan, Chao, Zhao, Ya, Zhang, Yanlong, Yin, Jun, Geng, Li, Mak, Pui In. A 3.57-mW 2.88-GHz Multi-Phase Injection-Locked Ring-VCO with a 200-kHz 1/f3 Phase Noise Corner[J]. IEEE Transactions on Circuits and Systems II - Express Briefs, 2022, 70(3), 865-869.
Authors:  Fan, Chao;  Zhao, Ya;  Zhang, Yanlong;  Yin, Jun;  Geng, Li; et al.
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:4.0/3.7 | Submit date：2023/01/30
Cmos  Ring Voltage-controlled Oscillator (Rvco)  Phase Noise  Flicker Noise  1/f3 Phase Noise Corner  Inherent Low-frequency Output  Multi-phase Injection Locking (Mpil)  Clock Generation  
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference Journal article
Yu Duan, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins. Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(12), 4799-4809.
Authors:  Yu Duan;  Chi-Hang Chan;  Yan Zhu;  Rui Paulo Martins
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:5.2/4.5 | Submit date：2023/01/30
Digital-regulated Supply Noise Cancellation (Dsnc)  Interference Reduction  Jitter  Phase Noise Cancellation (Pnc)  Phase-locked Loop  Phase-locked Loop (Pll)  Ring Voltage-controlled Oscillator (Rvco)  Supply Noise Suppression  
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop Journal article
Liu, Yueduo, Bao, Rongxin, Zhu, Zihao, Yang, Shiheng, Zhou, Xiong, Li, Qiang, Yin, Jun, Mak, Pui In. Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(2), 495-505.
Authors:  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2022/03/04
Voltage-controlled Oscillators  Jitter  Clocks  Phase Noise (Pn)  Topology  Performance Evaluation  Delays  Figure Of Merit (Fom)  Injection-locked Clock Multiplier (Ilcm)  Multiplying Delay-locked Loop (Mdll)  Power  Ring Voltage-controlled Oscillator (Rvco)  
A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT Journal article
Xiaofeng Yang, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins. A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(11), 3753-3763.
Authors:  Xiaofeng Yang;  Chi-Hang Chan;  Yan Zhu;  Rui Paulo Martins
Favorite | TC[WOS]:8 TC[Scopus]:8  IF:5.2/4.5 | Submit date：2021/03/04
Calibration-free  Discrete-time  Gain Tracking  Jitter  Open-loop  Phase Noise Cancellation (Pnc)  Phase-locked Loop (Pll)  Pvt  Reference Spur  Ring Voltage-controlled Oscillator (Rvco)  
A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM Journal article
Tongquan Jiang, Jun Yin, Pui-In Mak, Rui P. Martins. A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 66(2), 157-161.
Authors:  Tongquan Jiang;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:11 TC[Scopus]:13  IF:4.0/3.7 | Submit date：2019/02/14
Bootstrap (Bt)  Low Voltage  Non-overlapping Clock  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
Shiheng Yang, Jun Yin, Pui-In Mak, Rui P. Martins. A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs[J]. IEEE Journal of Solid-State Circuits, 2019, 54(1), 88-98.
Authors:  Shiheng Yang;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:27 TC[Scopus]:28  IF:4.6/5.6 | Submit date：2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 0.0056-mm² -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs Journal article
Yang, S., Yin, J., Mak, P. I., Martins, R. P.. A 0.0056-mm² -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 88-98.
Authors:  Yang, S.;  Yin, J.;  Mak, P. I.;  Martins, R. P.
Favorite | TC[WOS]:27 TC[Scopus]:28  IF:4.6/5.6 | Submit date：2022/01/24
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output Journal article
Jun Yin, Pui-In Mak, Franco Maloberti, Rui P. Martins. A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output[J]. IEEE Journal of Solid-State Circuits, 2016, 51(12), 2979-2991.
Authors:  Jun Yin;  Pui-In Mak;  Franco Maloberti;  Rui P. Martins
Favorite | TC[WOS]:25 TC[Scopus]:27 | Submit date：2019/02/11
1/f3 Phase Noise Corner  Divided Output  Flicker Noise  Impulse Sensitivity Function (Isf)  Phase Combiner  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Supply Voltage  Time-interleaved (Ti).  
A Time-Interleaved Ring-VCO with Reduced 1/f Phase Noise Corner, Extended Tuning Range and Inherent Divided Output Journal article
Yin, J., Mak, P. I., Maloberti, F., Martins, R. P.. A Time-Interleaved Ring-VCO with Reduced 1/f Phase Noise Corner, Extended Tuning Range and Inherent Divided Output[J]. IEEE Journal of Solid-State Circuits (JSSC), 2016, 2979-2991.
Authors:  Yin, J.;  Mak, P. I.;  Maloberti, F.;  Martins, R. P.
Favorite | TC[WOS]:25 TC[Scopus]:27  IF:4.6/5.6 | Submit date：2022/01/24
Ring Voltage-controlled Oscillator (Rvco)  Time-interleaved (Ti)  Impulse Sensitivity Function (Isf)  Phase Noise  1/f3 Phase Noise Corner  Phase Combiner  Divided Output  Supply Voltage  Flicker Noise