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Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
Liu J., Chan C.-H., Sin S.-W., Seng-Pan U., Martins R.P.. Accuracy-enhanced variance-based time-skew calibration using SAR as window detector[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(2), 481-485.
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite | TC[WOS]:13 TC[Scopus]:13  IF:2.8/2.8 | Submit date：2019/02/13
Bandwidth Mismatches  Split-digital To Analog Converter (Dac)  Successive-approximation-register (Sar) Analog-to-digital Converter (Adc)  Time-interleaved (Ti)  Variance Based  Window Detector (Wd)  
Split-SAR ADCs: Improved linearity with power and speed optimization Journal article
Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti. Split-SAR ADCs: Improved linearity with power and speed optimization[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22(2), 372-383.
Authors:  Yan Zhu;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U; et al.
Favorite | TC[WOS]:44 TC[Scopus]:56 | Submit date：2018/10/30
Linearity Analysis  Linearity Calibration  Sar Adcs  Split Dac  Vcm-based Switching  
Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs Journal article
Zhu, Y., Chio, U. F., Wei, H. G., Sin, S. W., Martins, R. P.. Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs[J]. VLSI Design, 2009, 1-10.
Authors:  Zhu, Y.;  Chio, U. F.;  Wei, H. G.;  Sin, S. W.;  Martins, R. P.
Favorite | TC[WOS]:14 TC[Scopus]:6 | Submit date：2022/01/24
Split Dac  Sar Adc  Linearity Analysis