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A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS
Journal article
Fan,Chao, Yu,Wei Han, Mak,Pui In, Martins,Rui P.. A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(12), 4850-4861.
Authors:
Fan,Chao
;
Yu,Wei Han
;
Mak,Pui In
;
Martins,Rui P.
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TC[WOS]:
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IF:
5.2
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Submit date：2021/03/09
Cmos
Current-mode-logic (Cml) Driver
Feed-forward Equalization (Ffe)
Four-level Pulse-amplitude Modulation (Pam-4)
Source-series-terminated (Sst) Driver
Sst-cml-hybrid (Sch) Driver
Transmitter (Tx)
