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A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter and -76.5-dBc Reference Spur Conference paper
Chen, Tianle, Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Zheng, Xuqiang, Guo, Xuan, Iizuka, Tetsuya, Mak, Pui In, Chen, Yong, Li, Bo. A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter and -76.5-dBc Reference Spur[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Chen, Tianle;  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Meng, Xianghe; et al.
Favorite | TC[Scopus]:0 | Submit date：2024/10/10
Phase Noise  Power Demand  Laser Mode Locking  Prototypes  Detectors  Crystals  Very Large Scale Integration  
A Fully Integrated 48-V GaN Driver Using Parallel-Multistep-Series Reconfigurable Switched-Capacitor Bank Achieving 7.7nC/mm2 On-Chip Bootstrap Driving Density Conference paper
Xuchu Mu, Yang Jiang, Rui Martins, Pui-In Mak. A Fully Integrated 48-V GaN Driver Using Parallel-Multistep-Series Reconfigurable Switched-Capacitor Bank Achieving 7.7nC/mm2 On-Chip Bootstrap Driving Density[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Xuchu Mu;  Yang Jiang;  Rui Martins;  Pui-In Mak
Favorite | TC[Scopus]:0 | Submit date：2024/08/29
Switching Frequency  Prototypes  Switches  Logic Gates  Very Large Scale Integration  Capacitance  System-on-chip  
A Regulation-Free Sub-0.5-V 16-/24-MHz Crystal Oscillator With 14.2-nJ Startup Energy and 31.8- μ W Steady-State Power Journal article
Lei, K. M., Mak, P. I., Law, M. K., Martins, R. P.. A Regulation-Free Sub-0.5-V 16-/24-MHz Crystal Oscillator With 14.2-nJ Startup Energy and 31.8- μ W Steady-State Power[J]. IEEE Journal of Solid-State Circuits, 2018, 2624-2635.
Authors:  Lei, K. M.;  Mak, P. I.;  Law, M. K.;  Martins, R. P.
Favorite | TC[WOS]:21 TC[Scopus]:24  IF:4.6/5.6 | Submit date：2022/01/25
Crystals  Oscillators  Chirp  Batteries  Steady-state  Capacitance  Very Large Scale Integration  
A dual-output SC converter with dynamic power allocation for multicore application processors, Conference paper
Jiang, J., Lu, Y., Liu, X., Ki, W.-H., Mok, P. K. T., U, S.-P., Martins, R. P.. A dual-output SC converter with dynamic power allocation for multicore application processors,[C], 2018.
Authors:  Jiang, J.;  Lu, Y.;  Liu, X.;  Ki, W.-H.;  Mok, P. K. T.; et al.
Favorite |  | Submit date：2022/01/24
Solid state circuits  Dynamic scheduling  Resource management  Very large scale integration  
Standard cell library design with voltage scaling and transistor sizing for ultra-low-power biomedical applications Conference paper
Chio-In Ieong, Mingzhong Li, Man-Kay Law, Pui-In Mak, Mang-I Vai, Peng-Un Mak, Feng Wan, Rui P. Martins. Standard cell library design with voltage scaling and transistor sizing for ultra-low-power biomedical applications[C]:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2013.
Authors:  Chio-In Ieong;  Mingzhong Li;  Man-Kay Law;  Pui-In Mak;  Mang-I Vai; et al.
Favorite | TC[WOS]:1 TC[Scopus]:4 | Submit date：2018/12/24
Transistors  Capacitances  Libraries  Logic Gates  Very Large Scale Integration  Power Demand  Inverter