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A 5.99-GHz VCO with Wideband-Differential-Mode Second Harmonic Resonance Achieving - 138.9 dBc/Hz Phase Noise at an Offset of 10 MHz Journal article
Yang, Chaowei, Chen, Yong, Huang, Yunbo, Martins, Rui P., Mak, Pui In. A 5.99-GHz VCO with Wideband-Differential-Mode Second Harmonic Resonance Achieving - 138.9 dBc/Hz Phase Noise at an Offset of 10 MHz[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(11), 1267-1270.
Authors:  Yang, Chaowei;  Chen, Yong;  Huang, Yunbo;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:0/0 | Submit date：2024/11/05
1/f3 Pn Corner  Cmos  Figure-of-merit (Fom)  Impulse Sensitivity Function (Isf)  Phase Noise (Pn)  Voltage-controlled Oscillator (Vco)  Wideband-harmonic Shaping  
A 167-μW 71.7-dB SFDR 2.4-GHz BLE Receiver Using a Passive Quadrature Front End, a Double-Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D VCO Journal article
Shao, Haijun, Martins, Rui P., Mak, Pui In. A 167-μW 71.7-dB SFDR 2.4-GHz BLE Receiver Using a Passive Quadrature Front End, a Double-Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D VCO[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Shao, Haijun;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/11/05
Adjacent Channel  Bluetooth Low Energy (Ble)  Cascaded  Cmos  Double Balanced  Figure Of Merit (Fom)  Hybrid Coupler  Noise Figure (Nf)  Notching  Out Of Band (Oob)  Passive Intensive  Phase Noise (Pn)  Quadrature  Signal-to-noise Ratio (Snr)  Spurious-free Dynamic Range (Sfdr)  Ultra-low-power (Ulp)  Voltage-controlled Oscillator (Vco)  
Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal–oxide–semiconductor Journal article
Yang, Chaowei, Chen, Yong, Cheng, Kai, Stefano, Crovetti Paolo, Martins, Rui P., Mak, Pui In. Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal–oxide–semiconductor[J]. International Journal of Circuit Theory and Applications, 2024.
Authors:  Yang, Chaowei;  Chen, Yong;  Cheng, Kai;  Stefano, Crovetti Paolo;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:1.8/1.7 | Submit date：2024/08/05
Clock And Data Recovery (Cdr)  Cmos Figure-of-merit (Fom)  Figure-of-merit With Tuning And Area (Fomta)  Figure-of-merit With Tuning Range (Fomt)  Flicker (1/f)  Noise Noise Transfer Phase Noise (Pn)  Phase-locked Loop (Pll)  Quality Factor Switched-capacitor Array (Sca)  Thermal Noise Transformer Tuning Range (Tr)  Ultra-wide-tuning-range Voltage-controlled Oscillator (Vco)  
A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM Journal article
Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Feng, Chaoping, Chen, Tianle, Zhang, Xinming, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Iizuka, Tetsuya, Chen, Yong, Mak, Pui In, Han, Zhengsheng, Li, Bo. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551.
Authors:  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Feng, Chaoping;  Chen, Tianle; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2  IF:0/0 | Submit date：2024/05/16
Double Sampling (Ds)  Figure Of Merit (Fom)  Frequency Synthesizer  Low Jitter  Low Spur  Phase Detector (Pd)  Phase-locked Loop (Pll)  Phase Noise (Pn)  Reference Sampling (Rs)  Subsampling (Ss)  Phase Locked Loops  Type-i  
A 54.6-65.1 GHz Multi-Path-Synchronized 16-Core Oscillator Achieving -131.4 dBc/Hz PN and 195.8 dBc/Hz FoMT at 10 MHz Offset in 65nm CMOS Conference paper
Zhan, Xiangxun, Yin, Jun, Martins, Rui P., Mak, Pui In. A 54.6-65.1 GHz Multi-Path-Synchronized 16-Core Oscillator Achieving -131.4 dBc/Hz PN and 195.8 dBc/Hz FoMT at 10 MHz Offset in 65nm CMOS[C]:IEEE Computer Society, 2024, 321-324.
Authors:  Zhan, Xiangxun;  Yin, Jun;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[Scopus]:0 | Submit date：2024/12/05
Figure Of Merit (Fom)  Millimeter Wave  Multiple Cores  Oscillator  Phase Noise (Pn)  Pn Penalty  
Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL Journal article
Song, Jingrun, Yang, Xinyu, Liu, Jiaxu, Liu, Yueduo, Zhu, Zihao, Han, Zhengxuan, Zhang, Zehao, Liu, Jiaxin, Zhang, Hongshuai, Yin, Jun, Mak, Pui In, Yang, Shiheng. Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
Authors:  Song, Jingrun;  Yang, Xinyu;  Liu, Jiaxu;  Liu, Yueduo;  Zhu, Zihao; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/12/26
Charge-sharing integrator  digital PLL (DPLL)  digitally controlled oscillator (DCO)  hybrid PLL (HPLL)  jitter  multi-rate  nonlinearity  phase noise (PN)  prediction  spectrum  spur  
A 12.9-to-24 GHz Dual-Mode Multi-Coil VCO Achieving 199.2 dBc/Hz Peak FoMT in 65-nm CMOS Journal article
Zhao, Ya, Fan, Chao, Peng, Yuanxing, Liang, Chenglong, Yin, Jun, Mak, Pui In, Geng, Li. A 12.9-to-24 GHz Dual-Mode Multi-Coil VCO Achieving 199.2 dBc/Hz Peak FoMT in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(5), 2604-2608.
Authors:  Zhao, Ya;  Fan, Chao;  Peng, Yuanxing;  Liang, Chenglong;  Yin, Jun; et al.
Favorite | TC[WOS]:3 TC[Scopus]:2  IF:4.0/3.7 | Submit date：2024/05/16
Couplings  Dual-core  Dual-mode  Frequency Tuning Range (Ftr)  Inductance  Layout  Millimeter-wave (Mm-wave)  Mode-switching  Multi-coil  Phase Noise (Pn)  Transformer Cores  Transformers  Tuning  Voltage-controlled Oscillator (Vco)  Voltage-controlled Oscillators  
Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion Journal article
Meng, Xi, Li, Haoran, Chen, Peng, Yin, Jun, Mak, Pui In, Martins, Rui P.. Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 5110-5123.
Authors:  Meng, Xi;  Li, Haoran;  Chen, Peng;  Yin, Jun;  Mak, Pui In; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:5.2/4.5 | Submit date：2024/02/22
Dual-core Coupled  Flicker Noise Upconversion  Inverse-class-f (Class-f-1)  Phase Noise (Pn)  Second Harmonic Resonance  Switched Capacitor  Voltage-controlled Oscillator (Vco)  
A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2nd-Harmonic Output Conference paper
Huang, Yunbo, Chen, Yong, Yang, Chaowei, Mak, Pui In, Martins, Rui P.. A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2nd-Harmonic Output[C], USA:Institute of Electrical and Electronics Engineers Inc., 2023.
Authors:  Huang, Yunbo;  Chen, Yong;  Yang, Chaowei;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:0 TC[Scopus]:2 | Submit date：2024/02/23
1/f3pn Corner  Cmos  Common-mode (Cm) Resonance  Figure-of-merit (Fom)  Flicker (1/f) Noise  Impulse Sensitivity Function (Isf)  Noise Transfer  Phase Noise (Pn)  Quality Factor  Thermal Noise  Tuning Range (Tr)  Voltage-controlled Oscillator (Vco)  
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop Journal article
Liu, Yueduo, Bao, Rongxin, Zhu, Zihao, Yang, Shiheng, Zhou, Xiong, Li, Qiang, Yin, Jun, Mak, Pui In. Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(2), 495-505.
Authors:  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2022/03/04
Voltage-controlled Oscillators  Jitter  Clocks  Phase Noise (Pn)  Topology  Performance Evaluation  Delays  Figure Of Merit (Fom)  Injection-locked Clock Multiplier (Ilcm)  Multiplying Delay-locked Loop (Mdll)  Power  Ring Voltage-controlled Oscillator (Rvco)