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A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique Conference paper
Rui Wang, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Zhihua Wang, Rui Paulo Martins. A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique[C], 2012, 265-268.
Authors:  Rui Wang;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Zhihua Wang; et al.
Favorite | TC[Scopus]:16 | Submit date：2019/02/11
Sar Adc  Pipelined  Digital Calibration  Op-amp Sharing  
A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS Conference paper
Guohe Yin, He-Gong Wei, U–Fat Chio, Sai-Weng Sin, Seng-Pan U, Zhihua Wang, Rui Paulo Martins. A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS[C], 2012, 377-380.
Authors:  Guohe Yin;  He-Gong Wei;  U–Fat Chio;  Sai-Weng Sin;  Seng-Pan U; et al.
Favorite | TC[Scopus]:7 | Submit date：2019/02/11
Analgo-to-digital Converter  Successive Approximation Register  Ultra-low Power  Sensor Applications