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A 2.63 μw ECG Processor with Adaptive Arrhythmia Detection and Data Compression for Implantable Cardiac Monitoring Device Journal article
Yin, Yue, Abubakar, Syed Muhammad, Tan, Songyao, Shi, Jiahua, Yang, Peilin, Yang, Wendi, Jiang, Hanjun, Wang, Zhihua, Jia, Wen, Ua, Seng Pan. A 2.63 μw ECG Processor with Adaptive Arrhythmia Detection and Data Compression for Implantable Cardiac Monitoring Device[J]. IEEE Transactions on Biomedical Circuits and Systems, 2021, 15(4), 777-790.
Authors:  Yin, Yue;  Abubakar, Syed Muhammad;  Tan, Songyao;  Shi, Jiahua;  Yang, Peilin; et al.
Favorite | TC[WOS]:24 TC[Scopus]:30  IF:3.8/4.8 | Submit date：2021/12/08
Adaptive Arrhythmia Detection  Data Compression  Ecg Processor  Implantable Cardiac Monitoring  Swinging Door Trending  
SE5: Making a Career Choice Other
2021-02-13
Authors:  Daly, Denis;  Lulec, Zeynep;  Yazicigil, Rabia Tugce;  Burdett, Alison;  Mandal, Rituparna; et al.
Favorite | TC[Scopus]:0 | Submit date：2021/12/07
Reconfigurable bidirectional wireless charging transceiver Patent
专利类型: 发明专利 Invention, 专利号: US10256661B1, 申请日期: 2017-12-15, 公开日期: 2019-04-09
Authors:  Yan Lu;  Mo Huang;  Seng Pan U;  Rui Paulo Da Silva Martins
Favorite |  | Submit date：2020/06/04
A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS Conference paper
Wang B., Sin S.-W., Seng-Pan U., Malobertr F., MartinMartinss R.P.. A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS[C], 2019, 207-208.
Authors:  Wang B.;  Sin S.-W.;  Seng-Pan U.;  Malobertr F.;  MartinMartinss R.P.
Favorite | TC[WOS]:44 TC[Scopus]:12 | Submit date：2019/02/11
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
Xing D., Zhu Y., Chan C.-H., Maloberti F., Seng-Pan U., Martins R.P.. Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(2), 489-501.
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.; et al.
Favorite | TC[WOS]:2 TC[Scopus]:5  IF:5.2/4.5 | Submit date：2019/02/11
Reference Interference  Sar Adc  Time-interleaved Scheme  Two-step Sar Conversion  
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
Liu J., Chan C.-H., Sin S.-W., Seng-Pan U., Martins R.P.. Accuracy-enhanced variance-based time-skew calibration using SAR as window detector[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(2), 481-485.
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite | TC[WOS]:13 TC[Scopus]:13  IF:2.8/2.8 | Submit date：2019/02/13
Bandwidth Mismatches  Split-digital To Analog Converter (Dac)  Successive-approximation-register (Sar) Analog-to-digital Converter (Adc)  Time-interleaved (Ti)  Variance Based  Window Detector (Wd)  
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler Conference paper
Jiang W., Zhu Y., Chan C.-H., Murmann B., Seng-Pan U., Martins R.P.. A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler[C], 2018, 235-238.
Authors:  Jiang W.;  Zhu Y.;  Chan C.-H.;  Murmann B.;  Seng-Pan U.; et al.
Favorite | TC[WOS]:4 TC[Scopus]:5 | Submit date：2019/02/11
Background Calibration  Current Integrating Sampler  Time-interleaved Adc  Timing Skew  
A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems Conference paper
Mao F., Lu Y., Seng-Pan U., Martins R.P.. A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems[C], 2018, 1-4.
Authors:  Mao F.;  Lu Y.;  Seng-Pan U.;  Martins R.P.
Favorite | TC[WOS]:1 TC[Scopus]:3 | Submit date：2019/02/11
Delay Compensation  Feedback Loop  Implantable Medical Devices  Real Time  Voltage Doubler  Wireless Power Transfer  
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS Journal article
Qiu, Lei, Tang, Kai, Zheng, Yuanjin, Siek, Liter, Zhu, Yan, U, Seng-Pan. A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26(3), 572-583.
Authors:  Qiu, Lei;  Tang, Kai;  Zheng, Yuanjin;  Siek, Liter;  Zhu, Yan; et al.
Favorite | TC[WOS]:15 TC[Scopus]:16  IF:2.8/2.8 | Submit date：2018/10/30
Digital Background Calibration  Subradix-2  Successive Pproximation Register (Sar) Analog-to-digital Converters (Adcs)  Time Interleaved (Ti)  Time Skew  
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
Chan, Chi-Hang, Zhu, Yan, Zhang, Wai-Hong, Seng-Pan, U., Martins, Rui Paulo. A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53(3), 850-860.
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite | TC[WOS]:60 TC[Scopus]:66  IF:4.6/5.6 | Submit date：2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving