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A 28 nm 368 fJ/cycle, 0.43%/V Supply Sensitivity, FLL based RC Oscillator Featuring Positive TC Only Resistors and ΣM Based Trimming Journal article
Huang,Yunbo, Chen,Yong, Yang,Kaiyuan, Crovetti,Paolo, Mak,Pui In, Martins,Rui P.. A 28 nm 368 fJ/cycle, 0.43%/V Supply Sensitivity, FLL based RC Oscillator Featuring Positive TC Only Resistors and ΣM Based Trimming[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(11), 3950-3954.
Authors:  Huang,Yunbo;  Chen,Yong;  Yang,Kaiyuan;  Crovetti,Paolo;  Mak,Pui In; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.0/3.7 | Submit date：2023/08/03
Clocks  Cmos  Delta-sigma-modulator  Energy Efficiency  Frequency Inaccuracy  Frequency-locked-loop (Fll)  Generators  Oscillators  Rc Oscillator  Resistance  Resistors  Switched-capacitor Resistor  Switches  Temperature Coefficients  Voltage-controlled Oscillators  
A 0.5V 22.5ppm∘C Bandgap Voltage Reference with Leakage Current Injection for Curvature Correction Journal article
Chon-Fai Lee, Chi-Wa U, Rui P. Martins, Chi-Seng Lam. A 0.5V 22.5ppm∘C Bandgap Voltage Reference with Leakage Current Injection for Curvature Correction[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(10), 3897 - 3901.
Authors:  Chon-Fai Lee;  Chi-Wa U;  Rui P. Martins;  Chi-Seng Lam
Favorite | TC[WOS]:4 TC[Scopus]:6  IF:4.0/3.7 | Submit date：2023/08/03
Bandgap Voltage Reference  Clocks  Internet Of Things  Internet Of Things  Leakage Current Injection  Leakage Currents  Power Demand  Switched-capacitor Circuits  Temperature Coefficient  Temperature Measurement  Transistors  Voltage  
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop Journal article
Liu, Yueduo, Bao, Rongxin, Zhu, Zihao, Yang, Shiheng, Zhou, Xiong, Li, Qiang, Yin, Jun, Mak, Pui In. Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(2), 495-505.
Authors:  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2022/03/04
Voltage-controlled Oscillators  Jitter  Clocks  Phase Noise (Pn)  Topology  Performance Evaluation  Delays  Figure Of Merit (Fom)  Injection-locked Clock Multiplier (Ilcm)  Multiplying Delay-locked Loop (Mdll)  Power  Ring Voltage-controlled Oscillator (Rvco)  
Switched-Capacitor Bandgap Voltage Reference for IoT Applications Journal article
U, Chi Wa, Law, Man Kay, Lam, Chi Seng, Martins, Rui P.. Switched-Capacitor Bandgap Voltage Reference for IoT Applications[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(1), 16-29.
Authors:  U, Chi Wa;  Law, Man Kay;  Lam, Chi Seng;  Martins, Rui P.
Favorite | TC[WOS]:14 TC[Scopus]:17  IF:5.2/4.5 | Submit date：2021/09/20
Bandgap Voltage Reference  Capacitors  Clocks  Integrated Circuit Modeling  Internet Of Things  Low Power  Low Voltage  Power Demand  Resistance  Switched Capacitor Circuits  Temperature Coefficient.  Temperature Distribution  
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS Journal article
Zhao, Xiaoteng, Chen, Yong, Mak, Pui In, Martins, Rui P.. A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 57(2), 546-561.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:13  IF:4.6/5.6 | Submit date：2021/10/28
Acquisition Speed  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Clocks  Cmos  Detectors  Four-level Pulse Amplitude Modulation (Pam-4)  Frequency Detector (Fd)  Frequency Modulation  Hybrid Control Circuit (Hcc)  Jitter  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Logic Gates  Phase Detector (Pd)  Strobe Point (Sp).  Switches  Voltage-controlled Oscillators  
A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration Journal article
Guo, M., Mao, J., Sin,SS. W., Wei, H., Martins, R. P.. A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration[J]. IEEE Journal of Solid-State Circuits, 2020, 693-705.
Authors:  Guo, M.;  Mao, J.;  Sin,SS. W.;  Wei, H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
Calibration  Timing  Clocks  Impedance  Signal To Noise Ratio  Channel Estimation  Jitter  
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation Conference paper
Zheng, Z., Wei, W., Lagos, J., Martens, E., Zhu, Y., Chan, C. H., Craninckx, J., Martins, R. P.. 16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation[C], 2020.
Authors:  Zheng, Z.;  Wei, W.;  Lagos, J.;  Martens, E.;  Zhu, Y.; et al.
Favorite |  | Submit date：2022/01/25
Amplifiers  Analogue-digital Conversion  Calibration  Interpolation  Dynamic Pipelined Adc  Dynamic Pipelined Architecture  Linearized Dynamic Amplifier  Post-amplification Residue Generation Scheme  Residue Amplification  Complex Residue-transferring Realization  Residue Amplifier  Power Consumption  Sar Adc  Calibration Complexity  Aggressive Interpolation Factor  Flash Adc  Mm-wave 5g Receivers  Adc-based Serial Links  Power 5.5 Mw  Calibration  Quantization (Signal)  Clocks  System-on-chip  Interpolation  Prototype  
Multiplying DLLs Book chapter
出自: Phase-Locked Frequency Generation and Clocking: Architectures and circuits for modern wireless and wireline systems, INST ENGINEERING TECH-IET, MICHAEL FARADAY HOUSE, STEVENAGE, HERTS SG1 2AY, ENGLAND:Institution of Engineering and Technology, 2020, 页码:645-664
Authors:  Yang, Shiheng;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2021/12/03
Clocks  Delay Lock Loops  Jitter  Low-power Electronics  Multiplying Circuits  System-on-chip  Voltage-controlled Oscillators  
A 0.0018-mm2 153%-Locking-Range CML-Based Divider-by-2 with Tunable Self-Resonant Frequency Using an Auxiliary Negative-gm Cell Journal article
Zhao, X., Chen, Y., Mak, P. I., Martins, R. P.. A 0.0018-mm2 153%-Locking-Range CML-Based Divider-by-2 with Tunable Self-Resonant Frequency Using an Auxiliary Negative-gm Cell[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 3330-3339.
Authors:  Zhao, X.;  Chen, Y.;  Mak, P. I.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
Frequency conversion  Resonant frequency  Latches  Frequency measurement  Clocks  IP networks  Inductors  
A 0.0071-mm² 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis Journal article
Chen, Y., Mak, P. I., Yang, Z., Boon, C., Martins, R. P.. A 0.0071-mm² 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 1-14.
Authors:  Chen, Y.;  Mak, P. I.;  Yang, Z.;  Boon, C.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
Delays  Delay lines  Pulse width modulation  Frequency-domain analysis  Jitter  Transmitters  Clocks