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A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique Journal article
Wang,Lin, Chen,Yong, Yang,Chaowei, Zhao,Xiaoteng, Mak,Pui In, Maloberti,Franco, Martins,Rui P.. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(7), 2637-2650.
Authors:  ; et al.
Favorite | TC[WOS]:2 TC[Scopus]:5  IF:5.2/4.5 | Submit date：2023/08/03
Bang-bang Clock And Data Recovery (Bbcdr)  Wide Capture Range  Single Loop  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Deliberate Current Mismatch  Ring Oscillator (Ro)  R-2r Dac  Positive (Pnc)  Negative (Nnc) And Zero (Znc) Net Current  Cmos  Bang-bang Phase Detector (Bbpd)  
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS Journal article
Xiaoteng Zhao, Yong Chen, Lin Wang, Pui In Mak, Franco Maloberti, Rui P. Martins. A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2022, 57(5), 1358-1371.
Authors:  Xiaoteng Zhao;  Yong Chen;  Lin Wang;  Pui In Mak;  Franco Maloberti; et al.
Favorite | TC[WOS]:11 TC[Scopus]:16  IF:4.6/5.6 | Submit date：2022/05/13
And Zero Net Current (Znc)  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Cmos  Four-level Pulse-amplitude Modulation (Pam)  Frequency Detector (Fd)  Half-rate  Negative Net Current (Nnc)  Positive Net Current (Pnc)  Reference-less  
A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme Conference paper
Wang, Lin, Chen, Yong, Yang, Chaowei, Zhao, Xiaoteng, Mak, Pui In, Maloberti, Franco, Martins, Rui P.. A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme[C]:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2022.
Authors:  Wang, Lin;  Chen, Yong;  Yang, Chaowei;  Zhao, Xiaoteng;  Mak, Pui In; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1 | Submit date：2023/03/06
Hybrid Control Circuit (Hcc)  Deliberate Current Mismatch  Charge Pump (Cp)  Ring Oscillator (Ro)  R-2r Dac  Positive (Pnc)  Negative (Nnc)  Zero (Znc) Net Current  
A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS Conference paper
Zhao, Xiaoteng, Chen, Yong, Wang, Lin, Mak, Pui In, Maloberti, Franco, Martins, Rui P.. A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS[C], 2021, 131-134.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Wang, Lin;  Mak, Pui In;  Maloberti, Franco; et al.
Favorite | TC[WOS]:6 TC[Scopus]:9 | Submit date：2021/09/20
4-level Pulse Amplitude Modulation (Pam-4)  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Cmos  Frequency Detector (Fd)  Half-rate  Negative (Nnc) Net Current  Positive (Pnc)  Reference Less  Single Loop  Zero (Znc)